/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_DMA6_QM_REGS_H_
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#define ASIC_REG_DMA6_QM_REGS_H_
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/*
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*****************************************
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* DMA6_QM (Prototype: QMAN)
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*****************************************
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*/
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#define mmDMA6_QM_GLBL_CFG0 0x5C8000
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#define mmDMA6_QM_GLBL_CFG1 0x5C8004
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#define mmDMA6_QM_GLBL_PROT 0x5C8008
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#define mmDMA6_QM_GLBL_ERR_CFG 0x5C800C
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#define mmDMA6_QM_GLBL_SECURE_PROPS_0 0x5C8010
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#define mmDMA6_QM_GLBL_SECURE_PROPS_1 0x5C8014
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#define mmDMA6_QM_GLBL_SECURE_PROPS_2 0x5C8018
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#define mmDMA6_QM_GLBL_SECURE_PROPS_3 0x5C801C
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#define mmDMA6_QM_GLBL_SECURE_PROPS_4 0x5C8020
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#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_0 0x5C8024
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#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_1 0x5C8028
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#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_2 0x5C802C
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#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_3 0x5C8030
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#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_4 0x5C8034
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#define mmDMA6_QM_GLBL_STS0 0x5C8038
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#define mmDMA6_QM_GLBL_STS1_0 0x5C8040
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#define mmDMA6_QM_GLBL_STS1_1 0x5C8044
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#define mmDMA6_QM_GLBL_STS1_2 0x5C8048
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#define mmDMA6_QM_GLBL_STS1_3 0x5C804C
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#define mmDMA6_QM_GLBL_STS1_4 0x5C8050
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#define mmDMA6_QM_GLBL_MSG_EN_0 0x5C8054
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#define mmDMA6_QM_GLBL_MSG_EN_1 0x5C8058
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#define mmDMA6_QM_GLBL_MSG_EN_2 0x5C805C
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#define mmDMA6_QM_GLBL_MSG_EN_3 0x5C8060
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#define mmDMA6_QM_GLBL_MSG_EN_4 0x5C8068
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#define mmDMA6_QM_PQ_BASE_LO_0 0x5C8070
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#define mmDMA6_QM_PQ_BASE_LO_1 0x5C8074
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#define mmDMA6_QM_PQ_BASE_LO_2 0x5C8078
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#define mmDMA6_QM_PQ_BASE_LO_3 0x5C807C
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#define mmDMA6_QM_PQ_BASE_HI_0 0x5C8080
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#define mmDMA6_QM_PQ_BASE_HI_1 0x5C8084
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#define mmDMA6_QM_PQ_BASE_HI_2 0x5C8088
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#define mmDMA6_QM_PQ_BASE_HI_3 0x5C808C
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#define mmDMA6_QM_PQ_SIZE_0 0x5C8090
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#define mmDMA6_QM_PQ_SIZE_1 0x5C8094
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#define mmDMA6_QM_PQ_SIZE_2 0x5C8098
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#define mmDMA6_QM_PQ_SIZE_3 0x5C809C
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#define mmDMA6_QM_PQ_PI_0 0x5C80A0
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#define mmDMA6_QM_PQ_PI_1 0x5C80A4
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#define mmDMA6_QM_PQ_PI_2 0x5C80A8
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#define mmDMA6_QM_PQ_PI_3 0x5C80AC
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#define mmDMA6_QM_PQ_CI_0 0x5C80B0
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#define mmDMA6_QM_PQ_CI_1 0x5C80B4
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#define mmDMA6_QM_PQ_CI_2 0x5C80B8
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#define mmDMA6_QM_PQ_CI_3 0x5C80BC
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#define mmDMA6_QM_PQ_CFG0_0 0x5C80C0
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#define mmDMA6_QM_PQ_CFG0_1 0x5C80C4
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#define mmDMA6_QM_PQ_CFG0_2 0x5C80C8
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#define mmDMA6_QM_PQ_CFG0_3 0x5C80CC
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#define mmDMA6_QM_PQ_CFG1_0 0x5C80D0
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#define mmDMA6_QM_PQ_CFG1_1 0x5C80D4
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#define mmDMA6_QM_PQ_CFG1_2 0x5C80D8
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#define mmDMA6_QM_PQ_CFG1_3 0x5C80DC
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#define mmDMA6_QM_PQ_ARUSER_31_11_0 0x5C80E0
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#define mmDMA6_QM_PQ_ARUSER_31_11_1 0x5C80E4
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#define mmDMA6_QM_PQ_ARUSER_31_11_2 0x5C80E8
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#define mmDMA6_QM_PQ_ARUSER_31_11_3 0x5C80EC
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#define mmDMA6_QM_PQ_STS0_0 0x5C80F0
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#define mmDMA6_QM_PQ_STS0_1 0x5C80F4
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#define mmDMA6_QM_PQ_STS0_2 0x5C80F8
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#define mmDMA6_QM_PQ_STS0_3 0x5C80FC
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#define mmDMA6_QM_PQ_STS1_0 0x5C8100
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#define mmDMA6_QM_PQ_STS1_1 0x5C8104
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#define mmDMA6_QM_PQ_STS1_2 0x5C8108
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#define mmDMA6_QM_PQ_STS1_3 0x5C810C
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#define mmDMA6_QM_CQ_CFG0_0 0x5C8110
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#define mmDMA6_QM_CQ_CFG0_1 0x5C8114
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#define mmDMA6_QM_CQ_CFG0_2 0x5C8118
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#define mmDMA6_QM_CQ_CFG0_3 0x5C811C
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#define mmDMA6_QM_CQ_CFG0_4 0x5C8120
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#define mmDMA6_QM_CQ_CFG1_0 0x5C8124
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#define mmDMA6_QM_CQ_CFG1_1 0x5C8128
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#define mmDMA6_QM_CQ_CFG1_2 0x5C812C
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#define mmDMA6_QM_CQ_CFG1_3 0x5C8130
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#define mmDMA6_QM_CQ_CFG1_4 0x5C8134
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#define mmDMA6_QM_CQ_ARUSER_31_11_0 0x5C8138
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#define mmDMA6_QM_CQ_ARUSER_31_11_1 0x5C813C
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#define mmDMA6_QM_CQ_ARUSER_31_11_2 0x5C8140
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#define mmDMA6_QM_CQ_ARUSER_31_11_3 0x5C8144
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#define mmDMA6_QM_CQ_ARUSER_31_11_4 0x5C8148
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#define mmDMA6_QM_CQ_STS0_0 0x5C814C
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#define mmDMA6_QM_CQ_STS0_1 0x5C8150
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#define mmDMA6_QM_CQ_STS0_2 0x5C8154
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#define mmDMA6_QM_CQ_STS0_3 0x5C8158
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#define mmDMA6_QM_CQ_STS0_4 0x5C815C
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#define mmDMA6_QM_CQ_STS1_0 0x5C8160
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#define mmDMA6_QM_CQ_STS1_1 0x5C8164
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#define mmDMA6_QM_CQ_STS1_2 0x5C8168
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#define mmDMA6_QM_CQ_STS1_3 0x5C816C
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#define mmDMA6_QM_CQ_STS1_4 0x5C8170
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#define mmDMA6_QM_CQ_PTR_LO_0 0x5C8174
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#define mmDMA6_QM_CQ_PTR_HI_0 0x5C8178
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#define mmDMA6_QM_CQ_TSIZE_0 0x5C817C
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#define mmDMA6_QM_CQ_CTL_0 0x5C8180
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#define mmDMA6_QM_CQ_PTR_LO_1 0x5C8184
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#define mmDMA6_QM_CQ_PTR_HI_1 0x5C8188
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#define mmDMA6_QM_CQ_TSIZE_1 0x5C818C
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#define mmDMA6_QM_CQ_CTL_1 0x5C8190
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#define mmDMA6_QM_CQ_PTR_LO_2 0x5C8194
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#define mmDMA6_QM_CQ_PTR_HI_2 0x5C8198
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#define mmDMA6_QM_CQ_TSIZE_2 0x5C819C
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#define mmDMA6_QM_CQ_CTL_2 0x5C81A0
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#define mmDMA6_QM_CQ_PTR_LO_3 0x5C81A4
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#define mmDMA6_QM_CQ_PTR_HI_3 0x5C81A8
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#define mmDMA6_QM_CQ_TSIZE_3 0x5C81AC
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#define mmDMA6_QM_CQ_CTL_3 0x5C81B0
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#define mmDMA6_QM_CQ_PTR_LO_4 0x5C81B4
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#define mmDMA6_QM_CQ_PTR_HI_4 0x5C81B8
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#define mmDMA6_QM_CQ_TSIZE_4 0x5C81BC
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#define mmDMA6_QM_CQ_CTL_4 0x5C81C0
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#define mmDMA6_QM_CQ_PTR_LO_STS_0 0x5C81C4
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#define mmDMA6_QM_CQ_PTR_LO_STS_1 0x5C81C8
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#define mmDMA6_QM_CQ_PTR_LO_STS_2 0x5C81CC
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#define mmDMA6_QM_CQ_PTR_LO_STS_3 0x5C81D0
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#define mmDMA6_QM_CQ_PTR_LO_STS_4 0x5C81D4
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#define mmDMA6_QM_CQ_PTR_HI_STS_0 0x5C81D8
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#define mmDMA6_QM_CQ_PTR_HI_STS_1 0x5C81DC
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#define mmDMA6_QM_CQ_PTR_HI_STS_2 0x5C81E0
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#define mmDMA6_QM_CQ_PTR_HI_STS_3 0x5C81E4
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#define mmDMA6_QM_CQ_PTR_HI_STS_4 0x5C81E8
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#define mmDMA6_QM_CQ_TSIZE_STS_0 0x5C81EC
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#define mmDMA6_QM_CQ_TSIZE_STS_1 0x5C81F0
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#define mmDMA6_QM_CQ_TSIZE_STS_2 0x5C81F4
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#define mmDMA6_QM_CQ_TSIZE_STS_3 0x5C81F8
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#define mmDMA6_QM_CQ_TSIZE_STS_4 0x5C81FC
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#define mmDMA6_QM_CQ_CTL_STS_0 0x5C8200
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#define mmDMA6_QM_CQ_CTL_STS_1 0x5C8204
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#define mmDMA6_QM_CQ_CTL_STS_2 0x5C8208
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#define mmDMA6_QM_CQ_CTL_STS_3 0x5C820C
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#define mmDMA6_QM_CQ_CTL_STS_4 0x5C8210
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#define mmDMA6_QM_CQ_IFIFO_CNT_0 0x5C8214
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#define mmDMA6_QM_CQ_IFIFO_CNT_1 0x5C8218
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#define mmDMA6_QM_CQ_IFIFO_CNT_2 0x5C821C
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#define mmDMA6_QM_CQ_IFIFO_CNT_3 0x5C8220
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#define mmDMA6_QM_CQ_IFIFO_CNT_4 0x5C8224
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#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_0 0x5C8228
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#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_1 0x5C822C
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#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_2 0x5C8230
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#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_3 0x5C8234
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#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_4 0x5C8238
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#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_0 0x5C823C
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#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_1 0x5C8240
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#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_2 0x5C8244
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#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_3 0x5C8248
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#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_4 0x5C824C
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#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_0 0x5C8250
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#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_1 0x5C8254
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#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_2 0x5C8258
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#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_3 0x5C825C
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#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_4 0x5C8260
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#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_0 0x5C8264
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#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_1 0x5C8268
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#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_2 0x5C826C
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#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_3 0x5C8270
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#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_4 0x5C8274
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#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_0 0x5C8278
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#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_1 0x5C827C
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#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_2 0x5C8280
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#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_3 0x5C8284
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#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_4 0x5C8288
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#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_0 0x5C828C
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#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_1 0x5C8290
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#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_2 0x5C8294
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#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_3 0x5C8298
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#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_4 0x5C829C
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#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_0 0x5C82A0
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#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_1 0x5C82A4
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#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_2 0x5C82A8
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#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_3 0x5C82AC
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#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_4 0x5C82B0
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#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_0 0x5C82B4
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#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_1 0x5C82B8
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#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_2 0x5C82BC
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#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_3 0x5C82C0
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#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_4 0x5C82C4
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#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_0 0x5C82C8
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#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_1 0x5C82CC
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#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_2 0x5C82D0
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#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_3 0x5C82D4
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#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_4 0x5C82D8
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#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5C82E0
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#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5C82E4
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#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5C82E8
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#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5C82EC
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#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5C82F0
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#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5C82F4
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#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5C82F8
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#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5C82FC
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#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x5C8300
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#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x5C8304
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#define mmDMA6_QM_CP_FENCE0_RDATA_0 0x5C8308
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#define mmDMA6_QM_CP_FENCE0_RDATA_1 0x5C830C
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#define mmDMA6_QM_CP_FENCE0_RDATA_2 0x5C8310
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#define mmDMA6_QM_CP_FENCE0_RDATA_3 0x5C8314
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#define mmDMA6_QM_CP_FENCE0_RDATA_4 0x5C8318
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#define mmDMA6_QM_CP_FENCE1_RDATA_0 0x5C831C
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#define mmDMA6_QM_CP_FENCE1_RDATA_1 0x5C8320
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#define mmDMA6_QM_CP_FENCE1_RDATA_2 0x5C8324
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#define mmDMA6_QM_CP_FENCE1_RDATA_3 0x5C8328
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#define mmDMA6_QM_CP_FENCE1_RDATA_4 0x5C832C
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#define mmDMA6_QM_CP_FENCE2_RDATA_0 0x5C8330
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#define mmDMA6_QM_CP_FENCE2_RDATA_1 0x5C8334
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#define mmDMA6_QM_CP_FENCE2_RDATA_2 0x5C8338
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#define mmDMA6_QM_CP_FENCE2_RDATA_3 0x5C833C
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#define mmDMA6_QM_CP_FENCE2_RDATA_4 0x5C8340
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#define mmDMA6_QM_CP_FENCE3_RDATA_0 0x5C8344
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#define mmDMA6_QM_CP_FENCE3_RDATA_1 0x5C8348
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#define mmDMA6_QM_CP_FENCE3_RDATA_2 0x5C834C
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#define mmDMA6_QM_CP_FENCE3_RDATA_3 0x5C8350
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#define mmDMA6_QM_CP_FENCE3_RDATA_4 0x5C8354
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#define mmDMA6_QM_CP_FENCE0_CNT_0 0x5C8358
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#define mmDMA6_QM_CP_FENCE0_CNT_1 0x5C835C
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#define mmDMA6_QM_CP_FENCE0_CNT_2 0x5C8360
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#define mmDMA6_QM_CP_FENCE0_CNT_3 0x5C8364
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#define mmDMA6_QM_CP_FENCE0_CNT_4 0x5C8368
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#define mmDMA6_QM_CP_FENCE1_CNT_0 0x5C836C
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#define mmDMA6_QM_CP_FENCE1_CNT_1 0x5C8370
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#define mmDMA6_QM_CP_FENCE1_CNT_2 0x5C8374
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#define mmDMA6_QM_CP_FENCE1_CNT_3 0x5C8378
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#define mmDMA6_QM_CP_FENCE1_CNT_4 0x5C837C
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#define mmDMA6_QM_CP_FENCE2_CNT_0 0x5C8380
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#define mmDMA6_QM_CP_FENCE2_CNT_1 0x5C8384
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#define mmDMA6_QM_CP_FENCE2_CNT_2 0x5C8388
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#define mmDMA6_QM_CP_FENCE2_CNT_3 0x5C838C
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#define mmDMA6_QM_CP_FENCE2_CNT_4 0x5C8390
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#define mmDMA6_QM_CP_FENCE3_CNT_0 0x5C8394
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#define mmDMA6_QM_CP_FENCE3_CNT_1 0x5C8398
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#define mmDMA6_QM_CP_FENCE3_CNT_2 0x5C839C
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#define mmDMA6_QM_CP_FENCE3_CNT_3 0x5C83A0
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#define mmDMA6_QM_CP_FENCE3_CNT_4 0x5C83A4
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#define mmDMA6_QM_CP_STS_0 0x5C83A8
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#define mmDMA6_QM_CP_STS_1 0x5C83AC
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#define mmDMA6_QM_CP_STS_2 0x5C83B0
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#define mmDMA6_QM_CP_STS_3 0x5C83B4
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#define mmDMA6_QM_CP_STS_4 0x5C83B8
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#define mmDMA6_QM_CP_CURRENT_INST_LO_0 0x5C83BC
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#define mmDMA6_QM_CP_CURRENT_INST_LO_1 0x5C83C0
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#define mmDMA6_QM_CP_CURRENT_INST_LO_2 0x5C83C4
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#define mmDMA6_QM_CP_CURRENT_INST_LO_3 0x5C83C8
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#define mmDMA6_QM_CP_CURRENT_INST_LO_4 0x5C83CC
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#define mmDMA6_QM_CP_CURRENT_INST_HI_0 0x5C83D0
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#define mmDMA6_QM_CP_CURRENT_INST_HI_1 0x5C83D4
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#define mmDMA6_QM_CP_CURRENT_INST_HI_2 0x5C83D8
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#define mmDMA6_QM_CP_CURRENT_INST_HI_3 0x5C83DC
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#define mmDMA6_QM_CP_CURRENT_INST_HI_4 0x5C83E0
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#define mmDMA6_QM_CP_BARRIER_CFG_0 0x5C83F4
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#define mmDMA6_QM_CP_BARRIER_CFG_1 0x5C83F8
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#define mmDMA6_QM_CP_BARRIER_CFG_2 0x5C83FC
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#define mmDMA6_QM_CP_BARRIER_CFG_3 0x5C8400
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#define mmDMA6_QM_CP_BARRIER_CFG_4 0x5C8404
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#define mmDMA6_QM_CP_DBG_0_0 0x5C8408
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#define mmDMA6_QM_CP_DBG_0_1 0x5C840C
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#define mmDMA6_QM_CP_DBG_0_2 0x5C8410
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#define mmDMA6_QM_CP_DBG_0_3 0x5C8414
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#define mmDMA6_QM_CP_DBG_0_4 0x5C8418
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#define mmDMA6_QM_CP_ARUSER_31_11_0 0x5C841C
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#define mmDMA6_QM_CP_ARUSER_31_11_1 0x5C8420
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#define mmDMA6_QM_CP_ARUSER_31_11_2 0x5C8424
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#define mmDMA6_QM_CP_ARUSER_31_11_3 0x5C8428
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#define mmDMA6_QM_CP_ARUSER_31_11_4 0x5C842C
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#define mmDMA6_QM_CP_AWUSER_31_11_0 0x5C8430
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#define mmDMA6_QM_CP_AWUSER_31_11_1 0x5C8434
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#define mmDMA6_QM_CP_AWUSER_31_11_2 0x5C8438
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#define mmDMA6_QM_CP_AWUSER_31_11_3 0x5C843C
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#define mmDMA6_QM_CP_AWUSER_31_11_4 0x5C8440
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#define mmDMA6_QM_ARB_CFG_0 0x5C8A00
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#define mmDMA6_QM_ARB_CHOISE_Q_PUSH 0x5C8A04
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#define mmDMA6_QM_ARB_WRR_WEIGHT_0 0x5C8A08
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#define mmDMA6_QM_ARB_WRR_WEIGHT_1 0x5C8A0C
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#define mmDMA6_QM_ARB_WRR_WEIGHT_2 0x5C8A10
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#define mmDMA6_QM_ARB_WRR_WEIGHT_3 0x5C8A14
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#define mmDMA6_QM_ARB_CFG_1 0x5C8A18
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_0 0x5C8A20
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_1 0x5C8A24
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_2 0x5C8A28
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_3 0x5C8A2C
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_4 0x5C8A30
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_5 0x5C8A34
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_6 0x5C8A38
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_7 0x5C8A3C
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_8 0x5C8A40
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_9 0x5C8A44
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_10 0x5C8A48
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_11 0x5C8A4C
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_12 0x5C8A50
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_13 0x5C8A54
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_14 0x5C8A58
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_15 0x5C8A5C
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_16 0x5C8A60
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_17 0x5C8A64
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_18 0x5C8A68
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_19 0x5C8A6C
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_20 0x5C8A70
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_21 0x5C8A74
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_22 0x5C8A78
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_23 0x5C8A7C
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_24 0x5C8A80
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_25 0x5C8A84
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_26 0x5C8A88
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_27 0x5C8A8C
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_28 0x5C8A90
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_29 0x5C8A94
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_30 0x5C8A98
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#define mmDMA6_QM_ARB_MST_AVAIL_CRED_31 0x5C8A9C
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#define mmDMA6_QM_ARB_MST_CRED_INC 0x5C8AA0
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x5C8AA4
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x5C8AA8
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x5C8AAC
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x5C8AB0
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x5C8AB4
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x5C8AB8
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x5C8ABC
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x5C8AC0
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x5C8AC4
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x5C8AC8
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x5C8ACC
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x5C8AD0
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x5C8AD4
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x5C8AD8
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x5C8ADC
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x5C8AE0
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x5C8AE4
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x5C8AE8
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x5C8AEC
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x5C8AF0
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x5C8AF4
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x5C8AF8
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x5C8AFC
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x5C8B00
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x5C8B04
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x5C8B08
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x5C8B0C
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x5C8B10
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x5C8B14
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x5C8B18
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x5C8B1C
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#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x5C8B20
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#define mmDMA6_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x5C8B28
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#define mmDMA6_QM_ARB_MST_SLAVE_EN 0x5C8B2C
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#define mmDMA6_QM_ARB_MST_QUIET_PER 0x5C8B34
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#define mmDMA6_QM_ARB_SLV_CHOISE_WDT 0x5C8B38
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#define mmDMA6_QM_ARB_SLV_ID 0x5C8B3C
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#define mmDMA6_QM_ARB_MSG_MAX_INFLIGHT 0x5C8B44
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#define mmDMA6_QM_ARB_MSG_AWUSER_31_11 0x5C8B48
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#define mmDMA6_QM_ARB_MSG_AWUSER_SEC_PROP 0x5C8B4C
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#define mmDMA6_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x5C8B50
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#define mmDMA6_QM_ARB_BASE_LO 0x5C8B54
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#define mmDMA6_QM_ARB_BASE_HI 0x5C8B58
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#define mmDMA6_QM_ARB_STATE_STS 0x5C8B80
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#define mmDMA6_QM_ARB_CHOISE_FULLNESS_STS 0x5C8B84
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#define mmDMA6_QM_ARB_MSG_STS 0x5C8B88
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#define mmDMA6_QM_ARB_SLV_CHOISE_Q_HEAD 0x5C8B8C
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#define mmDMA6_QM_ARB_ERR_CAUSE 0x5C8B9C
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#define mmDMA6_QM_ARB_ERR_MSG_EN 0x5C8BA0
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#define mmDMA6_QM_ARB_ERR_STS_DRP 0x5C8BA8
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#define mmDMA6_QM_ARB_MST_CRED_STS_0 0x5C8BB0
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#define mmDMA6_QM_ARB_MST_CRED_STS_1 0x5C8BB4
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#define mmDMA6_QM_ARB_MST_CRED_STS_2 0x5C8BB8
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#define mmDMA6_QM_ARB_MST_CRED_STS_3 0x5C8BBC
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#define mmDMA6_QM_ARB_MST_CRED_STS_4 0x5C8BC0
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#define mmDMA6_QM_ARB_MST_CRED_STS_5 0x5C8BC4
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#define mmDMA6_QM_ARB_MST_CRED_STS_6 0x5C8BC8
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#define mmDMA6_QM_ARB_MST_CRED_STS_7 0x5C8BCC
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#define mmDMA6_QM_ARB_MST_CRED_STS_8 0x5C8BD0
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#define mmDMA6_QM_ARB_MST_CRED_STS_9 0x5C8BD4
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#define mmDMA6_QM_ARB_MST_CRED_STS_10 0x5C8BD8
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#define mmDMA6_QM_ARB_MST_CRED_STS_11 0x5C8BDC
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#define mmDMA6_QM_ARB_MST_CRED_STS_12 0x5C8BE0
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#define mmDMA6_QM_ARB_MST_CRED_STS_13 0x5C8BE4
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#define mmDMA6_QM_ARB_MST_CRED_STS_14 0x5C8BE8
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#define mmDMA6_QM_ARB_MST_CRED_STS_15 0x5C8BEC
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#define mmDMA6_QM_ARB_MST_CRED_STS_16 0x5C8BF0
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#define mmDMA6_QM_ARB_MST_CRED_STS_17 0x5C8BF4
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#define mmDMA6_QM_ARB_MST_CRED_STS_18 0x5C8BF8
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#define mmDMA6_QM_ARB_MST_CRED_STS_19 0x5C8BFC
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#define mmDMA6_QM_ARB_MST_CRED_STS_20 0x5C8C00
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#define mmDMA6_QM_ARB_MST_CRED_STS_21 0x5C8C04
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#define mmDMA6_QM_ARB_MST_CRED_STS_22 0x5C8C08
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#define mmDMA6_QM_ARB_MST_CRED_STS_23 0x5C8C0C
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#define mmDMA6_QM_ARB_MST_CRED_STS_24 0x5C8C10
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#define mmDMA6_QM_ARB_MST_CRED_STS_25 0x5C8C14
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#define mmDMA6_QM_ARB_MST_CRED_STS_26 0x5C8C18
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#define mmDMA6_QM_ARB_MST_CRED_STS_27 0x5C8C1C
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#define mmDMA6_QM_ARB_MST_CRED_STS_28 0x5C8C20
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#define mmDMA6_QM_ARB_MST_CRED_STS_29 0x5C8C24
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#define mmDMA6_QM_ARB_MST_CRED_STS_30 0x5C8C28
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#define mmDMA6_QM_ARB_MST_CRED_STS_31 0x5C8C2C
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#define mmDMA6_QM_CGM_CFG 0x5C8C70
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#define mmDMA6_QM_CGM_STS 0x5C8C74
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#define mmDMA6_QM_CGM_CFG1 0x5C8C78
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#define mmDMA6_QM_LOCAL_RANGE_BASE 0x5C8C80
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#define mmDMA6_QM_LOCAL_RANGE_SIZE 0x5C8C84
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#define mmDMA6_QM_CSMR_STRICT_PRIO_CFG 0x5C8C90
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#define mmDMA6_QM_HBW_RD_RATE_LIM_CFG_1 0x5C8C94
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#define mmDMA6_QM_LBW_WR_RATE_LIM_CFG_0 0x5C8C98
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#define mmDMA6_QM_LBW_WR_RATE_LIM_CFG_1 0x5C8C9C
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#define mmDMA6_QM_HBW_RD_RATE_LIM_CFG_0 0x5C8CA0
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#define mmDMA6_QM_GLBL_AXCACHE 0x5C8CA4
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#define mmDMA6_QM_IND_GW_APB_CFG 0x5C8CB0
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#define mmDMA6_QM_IND_GW_APB_WDATA 0x5C8CB4
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#define mmDMA6_QM_IND_GW_APB_RDATA 0x5C8CB8
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#define mmDMA6_QM_IND_GW_APB_STATUS 0x5C8CBC
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#define mmDMA6_QM_GLBL_ERR_ADDR_LO 0x5C8CD0
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#define mmDMA6_QM_GLBL_ERR_ADDR_HI 0x5C8CD4
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#define mmDMA6_QM_GLBL_ERR_WDATA 0x5C8CD8
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#define mmDMA6_QM_GLBL_MEM_INIT_BUSY 0x5C8D00
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#endif /* ASIC_REG_DMA6_QM_REGS_H_ */
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