/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_DMA5_QM_REGS_H_
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#define ASIC_REG_DMA5_QM_REGS_H_
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/*
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*****************************************
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* DMA5_QM (Prototype: QMAN)
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*****************************************
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*/
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#define mmDMA5_QM_GLBL_CFG0 0x5A8000
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#define mmDMA5_QM_GLBL_CFG1 0x5A8004
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#define mmDMA5_QM_GLBL_PROT 0x5A8008
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#define mmDMA5_QM_GLBL_ERR_CFG 0x5A800C
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#define mmDMA5_QM_GLBL_SECURE_PROPS_0 0x5A8010
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#define mmDMA5_QM_GLBL_SECURE_PROPS_1 0x5A8014
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#define mmDMA5_QM_GLBL_SECURE_PROPS_2 0x5A8018
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#define mmDMA5_QM_GLBL_SECURE_PROPS_3 0x5A801C
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#define mmDMA5_QM_GLBL_SECURE_PROPS_4 0x5A8020
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#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_0 0x5A8024
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#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_1 0x5A8028
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#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_2 0x5A802C
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#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_3 0x5A8030
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#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_4 0x5A8034
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#define mmDMA5_QM_GLBL_STS0 0x5A8038
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#define mmDMA5_QM_GLBL_STS1_0 0x5A8040
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#define mmDMA5_QM_GLBL_STS1_1 0x5A8044
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#define mmDMA5_QM_GLBL_STS1_2 0x5A8048
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#define mmDMA5_QM_GLBL_STS1_3 0x5A804C
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#define mmDMA5_QM_GLBL_STS1_4 0x5A8050
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#define mmDMA5_QM_GLBL_MSG_EN_0 0x5A8054
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#define mmDMA5_QM_GLBL_MSG_EN_1 0x5A8058
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#define mmDMA5_QM_GLBL_MSG_EN_2 0x5A805C
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#define mmDMA5_QM_GLBL_MSG_EN_3 0x5A8060
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#define mmDMA5_QM_GLBL_MSG_EN_4 0x5A8068
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#define mmDMA5_QM_PQ_BASE_LO_0 0x5A8070
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#define mmDMA5_QM_PQ_BASE_LO_1 0x5A8074
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#define mmDMA5_QM_PQ_BASE_LO_2 0x5A8078
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#define mmDMA5_QM_PQ_BASE_LO_3 0x5A807C
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#define mmDMA5_QM_PQ_BASE_HI_0 0x5A8080
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#define mmDMA5_QM_PQ_BASE_HI_1 0x5A8084
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#define mmDMA5_QM_PQ_BASE_HI_2 0x5A8088
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#define mmDMA5_QM_PQ_BASE_HI_3 0x5A808C
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#define mmDMA5_QM_PQ_SIZE_0 0x5A8090
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#define mmDMA5_QM_PQ_SIZE_1 0x5A8094
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#define mmDMA5_QM_PQ_SIZE_2 0x5A8098
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#define mmDMA5_QM_PQ_SIZE_3 0x5A809C
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#define mmDMA5_QM_PQ_PI_0 0x5A80A0
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#define mmDMA5_QM_PQ_PI_1 0x5A80A4
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#define mmDMA5_QM_PQ_PI_2 0x5A80A8
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#define mmDMA5_QM_PQ_PI_3 0x5A80AC
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#define mmDMA5_QM_PQ_CI_0 0x5A80B0
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#define mmDMA5_QM_PQ_CI_1 0x5A80B4
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#define mmDMA5_QM_PQ_CI_2 0x5A80B8
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#define mmDMA5_QM_PQ_CI_3 0x5A80BC
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#define mmDMA5_QM_PQ_CFG0_0 0x5A80C0
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#define mmDMA5_QM_PQ_CFG0_1 0x5A80C4
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#define mmDMA5_QM_PQ_CFG0_2 0x5A80C8
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#define mmDMA5_QM_PQ_CFG0_3 0x5A80CC
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#define mmDMA5_QM_PQ_CFG1_0 0x5A80D0
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#define mmDMA5_QM_PQ_CFG1_1 0x5A80D4
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#define mmDMA5_QM_PQ_CFG1_2 0x5A80D8
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#define mmDMA5_QM_PQ_CFG1_3 0x5A80DC
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#define mmDMA5_QM_PQ_ARUSER_31_11_0 0x5A80E0
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#define mmDMA5_QM_PQ_ARUSER_31_11_1 0x5A80E4
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#define mmDMA5_QM_PQ_ARUSER_31_11_2 0x5A80E8
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#define mmDMA5_QM_PQ_ARUSER_31_11_3 0x5A80EC
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#define mmDMA5_QM_PQ_STS0_0 0x5A80F0
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#define mmDMA5_QM_PQ_STS0_1 0x5A80F4
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#define mmDMA5_QM_PQ_STS0_2 0x5A80F8
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#define mmDMA5_QM_PQ_STS0_3 0x5A80FC
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#define mmDMA5_QM_PQ_STS1_0 0x5A8100
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#define mmDMA5_QM_PQ_STS1_1 0x5A8104
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#define mmDMA5_QM_PQ_STS1_2 0x5A8108
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#define mmDMA5_QM_PQ_STS1_3 0x5A810C
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#define mmDMA5_QM_CQ_CFG0_0 0x5A8110
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#define mmDMA5_QM_CQ_CFG0_1 0x5A8114
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#define mmDMA5_QM_CQ_CFG0_2 0x5A8118
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#define mmDMA5_QM_CQ_CFG0_3 0x5A811C
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#define mmDMA5_QM_CQ_CFG0_4 0x5A8120
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#define mmDMA5_QM_CQ_CFG1_0 0x5A8124
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#define mmDMA5_QM_CQ_CFG1_1 0x5A8128
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#define mmDMA5_QM_CQ_CFG1_2 0x5A812C
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#define mmDMA5_QM_CQ_CFG1_3 0x5A8130
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#define mmDMA5_QM_CQ_CFG1_4 0x5A8134
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#define mmDMA5_QM_CQ_ARUSER_31_11_0 0x5A8138
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#define mmDMA5_QM_CQ_ARUSER_31_11_1 0x5A813C
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#define mmDMA5_QM_CQ_ARUSER_31_11_2 0x5A8140
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#define mmDMA5_QM_CQ_ARUSER_31_11_3 0x5A8144
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#define mmDMA5_QM_CQ_ARUSER_31_11_4 0x5A8148
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#define mmDMA5_QM_CQ_STS0_0 0x5A814C
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#define mmDMA5_QM_CQ_STS0_1 0x5A8150
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#define mmDMA5_QM_CQ_STS0_2 0x5A8154
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#define mmDMA5_QM_CQ_STS0_3 0x5A8158
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#define mmDMA5_QM_CQ_STS0_4 0x5A815C
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#define mmDMA5_QM_CQ_STS1_0 0x5A8160
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#define mmDMA5_QM_CQ_STS1_1 0x5A8164
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#define mmDMA5_QM_CQ_STS1_2 0x5A8168
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#define mmDMA5_QM_CQ_STS1_3 0x5A816C
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#define mmDMA5_QM_CQ_STS1_4 0x5A8170
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#define mmDMA5_QM_CQ_PTR_LO_0 0x5A8174
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#define mmDMA5_QM_CQ_PTR_HI_0 0x5A8178
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#define mmDMA5_QM_CQ_TSIZE_0 0x5A817C
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#define mmDMA5_QM_CQ_CTL_0 0x5A8180
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#define mmDMA5_QM_CQ_PTR_LO_1 0x5A8184
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#define mmDMA5_QM_CQ_PTR_HI_1 0x5A8188
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#define mmDMA5_QM_CQ_TSIZE_1 0x5A818C
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#define mmDMA5_QM_CQ_CTL_1 0x5A8190
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#define mmDMA5_QM_CQ_PTR_LO_2 0x5A8194
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#define mmDMA5_QM_CQ_PTR_HI_2 0x5A8198
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#define mmDMA5_QM_CQ_TSIZE_2 0x5A819C
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#define mmDMA5_QM_CQ_CTL_2 0x5A81A0
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#define mmDMA5_QM_CQ_PTR_LO_3 0x5A81A4
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#define mmDMA5_QM_CQ_PTR_HI_3 0x5A81A8
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#define mmDMA5_QM_CQ_TSIZE_3 0x5A81AC
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#define mmDMA5_QM_CQ_CTL_3 0x5A81B0
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#define mmDMA5_QM_CQ_PTR_LO_4 0x5A81B4
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#define mmDMA5_QM_CQ_PTR_HI_4 0x5A81B8
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#define mmDMA5_QM_CQ_TSIZE_4 0x5A81BC
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#define mmDMA5_QM_CQ_CTL_4 0x5A81C0
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#define mmDMA5_QM_CQ_PTR_LO_STS_0 0x5A81C4
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#define mmDMA5_QM_CQ_PTR_LO_STS_1 0x5A81C8
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#define mmDMA5_QM_CQ_PTR_LO_STS_2 0x5A81CC
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#define mmDMA5_QM_CQ_PTR_LO_STS_3 0x5A81D0
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#define mmDMA5_QM_CQ_PTR_LO_STS_4 0x5A81D4
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#define mmDMA5_QM_CQ_PTR_HI_STS_0 0x5A81D8
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#define mmDMA5_QM_CQ_PTR_HI_STS_1 0x5A81DC
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#define mmDMA5_QM_CQ_PTR_HI_STS_2 0x5A81E0
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#define mmDMA5_QM_CQ_PTR_HI_STS_3 0x5A81E4
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#define mmDMA5_QM_CQ_PTR_HI_STS_4 0x5A81E8
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#define mmDMA5_QM_CQ_TSIZE_STS_0 0x5A81EC
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#define mmDMA5_QM_CQ_TSIZE_STS_1 0x5A81F0
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#define mmDMA5_QM_CQ_TSIZE_STS_2 0x5A81F4
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#define mmDMA5_QM_CQ_TSIZE_STS_3 0x5A81F8
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#define mmDMA5_QM_CQ_TSIZE_STS_4 0x5A81FC
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#define mmDMA5_QM_CQ_CTL_STS_0 0x5A8200
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#define mmDMA5_QM_CQ_CTL_STS_1 0x5A8204
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#define mmDMA5_QM_CQ_CTL_STS_2 0x5A8208
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#define mmDMA5_QM_CQ_CTL_STS_3 0x5A820C
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#define mmDMA5_QM_CQ_CTL_STS_4 0x5A8210
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#define mmDMA5_QM_CQ_IFIFO_CNT_0 0x5A8214
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#define mmDMA5_QM_CQ_IFIFO_CNT_1 0x5A8218
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#define mmDMA5_QM_CQ_IFIFO_CNT_2 0x5A821C
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#define mmDMA5_QM_CQ_IFIFO_CNT_3 0x5A8220
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#define mmDMA5_QM_CQ_IFIFO_CNT_4 0x5A8224
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#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_0 0x5A8228
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#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_1 0x5A822C
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#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_2 0x5A8230
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#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_3 0x5A8234
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#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_4 0x5A8238
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#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_0 0x5A823C
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#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_1 0x5A8240
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#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_2 0x5A8244
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#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_3 0x5A8248
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#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_4 0x5A824C
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#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_0 0x5A8250
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#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_1 0x5A8254
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#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_2 0x5A8258
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#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_3 0x5A825C
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#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_4 0x5A8260
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#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_0 0x5A8264
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#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_1 0x5A8268
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#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_2 0x5A826C
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#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_3 0x5A8270
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#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_4 0x5A8274
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#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_0 0x5A8278
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#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_1 0x5A827C
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#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_2 0x5A8280
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#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_3 0x5A8284
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#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_4 0x5A8288
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#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_0 0x5A828C
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#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_1 0x5A8290
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#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_2 0x5A8294
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#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_3 0x5A8298
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#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_4 0x5A829C
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#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_0 0x5A82A0
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#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_1 0x5A82A4
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#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_2 0x5A82A8
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#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_3 0x5A82AC
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#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_4 0x5A82B0
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#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_0 0x5A82B4
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#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_1 0x5A82B8
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#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_2 0x5A82BC
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#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_3 0x5A82C0
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#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_4 0x5A82C4
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#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_0 0x5A82C8
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#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_1 0x5A82CC
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#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_2 0x5A82D0
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#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_3 0x5A82D4
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#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_4 0x5A82D8
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#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5A82E0
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#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5A82E4
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#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5A82E8
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#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5A82EC
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#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5A82F0
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#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5A82F4
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#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5A82F8
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#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5A82FC
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#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x5A8300
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#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x5A8304
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#define mmDMA5_QM_CP_FENCE0_RDATA_0 0x5A8308
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#define mmDMA5_QM_CP_FENCE0_RDATA_1 0x5A830C
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#define mmDMA5_QM_CP_FENCE0_RDATA_2 0x5A8310
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#define mmDMA5_QM_CP_FENCE0_RDATA_3 0x5A8314
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#define mmDMA5_QM_CP_FENCE0_RDATA_4 0x5A8318
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#define mmDMA5_QM_CP_FENCE1_RDATA_0 0x5A831C
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#define mmDMA5_QM_CP_FENCE1_RDATA_1 0x5A8320
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#define mmDMA5_QM_CP_FENCE1_RDATA_2 0x5A8324
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#define mmDMA5_QM_CP_FENCE1_RDATA_3 0x5A8328
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#define mmDMA5_QM_CP_FENCE1_RDATA_4 0x5A832C
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#define mmDMA5_QM_CP_FENCE2_RDATA_0 0x5A8330
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#define mmDMA5_QM_CP_FENCE2_RDATA_1 0x5A8334
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#define mmDMA5_QM_CP_FENCE2_RDATA_2 0x5A8338
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#define mmDMA5_QM_CP_FENCE2_RDATA_3 0x5A833C
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#define mmDMA5_QM_CP_FENCE2_RDATA_4 0x5A8340
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#define mmDMA5_QM_CP_FENCE3_RDATA_0 0x5A8344
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#define mmDMA5_QM_CP_FENCE3_RDATA_1 0x5A8348
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#define mmDMA5_QM_CP_FENCE3_RDATA_2 0x5A834C
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#define mmDMA5_QM_CP_FENCE3_RDATA_3 0x5A8350
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#define mmDMA5_QM_CP_FENCE3_RDATA_4 0x5A8354
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#define mmDMA5_QM_CP_FENCE0_CNT_0 0x5A8358
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#define mmDMA5_QM_CP_FENCE0_CNT_1 0x5A835C
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#define mmDMA5_QM_CP_FENCE0_CNT_2 0x5A8360
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#define mmDMA5_QM_CP_FENCE0_CNT_3 0x5A8364
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#define mmDMA5_QM_CP_FENCE0_CNT_4 0x5A8368
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#define mmDMA5_QM_CP_FENCE1_CNT_0 0x5A836C
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#define mmDMA5_QM_CP_FENCE1_CNT_1 0x5A8370
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#define mmDMA5_QM_CP_FENCE1_CNT_2 0x5A8374
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#define mmDMA5_QM_CP_FENCE1_CNT_3 0x5A8378
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#define mmDMA5_QM_CP_FENCE1_CNT_4 0x5A837C
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#define mmDMA5_QM_CP_FENCE2_CNT_0 0x5A8380
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#define mmDMA5_QM_CP_FENCE2_CNT_1 0x5A8384
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#define mmDMA5_QM_CP_FENCE2_CNT_2 0x5A8388
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#define mmDMA5_QM_CP_FENCE2_CNT_3 0x5A838C
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#define mmDMA5_QM_CP_FENCE2_CNT_4 0x5A8390
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#define mmDMA5_QM_CP_FENCE3_CNT_0 0x5A8394
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#define mmDMA5_QM_CP_FENCE3_CNT_1 0x5A8398
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#define mmDMA5_QM_CP_FENCE3_CNT_2 0x5A839C
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#define mmDMA5_QM_CP_FENCE3_CNT_3 0x5A83A0
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#define mmDMA5_QM_CP_FENCE3_CNT_4 0x5A83A4
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#define mmDMA5_QM_CP_STS_0 0x5A83A8
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#define mmDMA5_QM_CP_STS_1 0x5A83AC
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#define mmDMA5_QM_CP_STS_2 0x5A83B0
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#define mmDMA5_QM_CP_STS_3 0x5A83B4
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#define mmDMA5_QM_CP_STS_4 0x5A83B8
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#define mmDMA5_QM_CP_CURRENT_INST_LO_0 0x5A83BC
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#define mmDMA5_QM_CP_CURRENT_INST_LO_1 0x5A83C0
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#define mmDMA5_QM_CP_CURRENT_INST_LO_2 0x5A83C4
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#define mmDMA5_QM_CP_CURRENT_INST_LO_3 0x5A83C8
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#define mmDMA5_QM_CP_CURRENT_INST_LO_4 0x5A83CC
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#define mmDMA5_QM_CP_CURRENT_INST_HI_0 0x5A83D0
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#define mmDMA5_QM_CP_CURRENT_INST_HI_1 0x5A83D4
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#define mmDMA5_QM_CP_CURRENT_INST_HI_2 0x5A83D8
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#define mmDMA5_QM_CP_CURRENT_INST_HI_3 0x5A83DC
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#define mmDMA5_QM_CP_CURRENT_INST_HI_4 0x5A83E0
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#define mmDMA5_QM_CP_BARRIER_CFG_0 0x5A83F4
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#define mmDMA5_QM_CP_BARRIER_CFG_1 0x5A83F8
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#define mmDMA5_QM_CP_BARRIER_CFG_2 0x5A83FC
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#define mmDMA5_QM_CP_BARRIER_CFG_3 0x5A8400
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#define mmDMA5_QM_CP_BARRIER_CFG_4 0x5A8404
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#define mmDMA5_QM_CP_DBG_0_0 0x5A8408
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#define mmDMA5_QM_CP_DBG_0_1 0x5A840C
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#define mmDMA5_QM_CP_DBG_0_2 0x5A8410
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#define mmDMA5_QM_CP_DBG_0_3 0x5A8414
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#define mmDMA5_QM_CP_DBG_0_4 0x5A8418
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#define mmDMA5_QM_CP_ARUSER_31_11_0 0x5A841C
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#define mmDMA5_QM_CP_ARUSER_31_11_1 0x5A8420
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#define mmDMA5_QM_CP_ARUSER_31_11_2 0x5A8424
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#define mmDMA5_QM_CP_ARUSER_31_11_3 0x5A8428
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#define mmDMA5_QM_CP_ARUSER_31_11_4 0x5A842C
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#define mmDMA5_QM_CP_AWUSER_31_11_0 0x5A8430
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#define mmDMA5_QM_CP_AWUSER_31_11_1 0x5A8434
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#define mmDMA5_QM_CP_AWUSER_31_11_2 0x5A8438
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#define mmDMA5_QM_CP_AWUSER_31_11_3 0x5A843C
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#define mmDMA5_QM_CP_AWUSER_31_11_4 0x5A8440
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#define mmDMA5_QM_ARB_CFG_0 0x5A8A00
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#define mmDMA5_QM_ARB_CHOISE_Q_PUSH 0x5A8A04
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#define mmDMA5_QM_ARB_WRR_WEIGHT_0 0x5A8A08
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#define mmDMA5_QM_ARB_WRR_WEIGHT_1 0x5A8A0C
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#define mmDMA5_QM_ARB_WRR_WEIGHT_2 0x5A8A10
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#define mmDMA5_QM_ARB_WRR_WEIGHT_3 0x5A8A14
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#define mmDMA5_QM_ARB_CFG_1 0x5A8A18
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_0 0x5A8A20
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_1 0x5A8A24
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_2 0x5A8A28
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_3 0x5A8A2C
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_4 0x5A8A30
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_5 0x5A8A34
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_6 0x5A8A38
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_7 0x5A8A3C
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_8 0x5A8A40
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_9 0x5A8A44
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_10 0x5A8A48
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_11 0x5A8A4C
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_12 0x5A8A50
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_13 0x5A8A54
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_14 0x5A8A58
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_15 0x5A8A5C
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_16 0x5A8A60
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_17 0x5A8A64
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_18 0x5A8A68
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_19 0x5A8A6C
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_20 0x5A8A70
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_21 0x5A8A74
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_22 0x5A8A78
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_23 0x5A8A7C
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_24 0x5A8A80
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_25 0x5A8A84
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_26 0x5A8A88
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_27 0x5A8A8C
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_28 0x5A8A90
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_29 0x5A8A94
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_30 0x5A8A98
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#define mmDMA5_QM_ARB_MST_AVAIL_CRED_31 0x5A8A9C
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#define mmDMA5_QM_ARB_MST_CRED_INC 0x5A8AA0
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x5A8AA4
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x5A8AA8
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x5A8AAC
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x5A8AB0
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x5A8AB4
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x5A8AB8
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x5A8ABC
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x5A8AC0
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x5A8AC4
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x5A8AC8
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x5A8ACC
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x5A8AD0
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x5A8AD4
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x5A8AD8
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x5A8ADC
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x5A8AE0
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x5A8AE4
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x5A8AE8
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x5A8AEC
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x5A8AF0
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x5A8AF4
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x5A8AF8
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x5A8AFC
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x5A8B00
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x5A8B04
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x5A8B08
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x5A8B0C
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x5A8B10
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x5A8B14
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x5A8B18
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x5A8B1C
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#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x5A8B20
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#define mmDMA5_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x5A8B28
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#define mmDMA5_QM_ARB_MST_SLAVE_EN 0x5A8B2C
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#define mmDMA5_QM_ARB_MST_QUIET_PER 0x5A8B34
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#define mmDMA5_QM_ARB_SLV_CHOISE_WDT 0x5A8B38
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#define mmDMA5_QM_ARB_SLV_ID 0x5A8B3C
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#define mmDMA5_QM_ARB_MSG_MAX_INFLIGHT 0x5A8B44
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#define mmDMA5_QM_ARB_MSG_AWUSER_31_11 0x5A8B48
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#define mmDMA5_QM_ARB_MSG_AWUSER_SEC_PROP 0x5A8B4C
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#define mmDMA5_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x5A8B50
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#define mmDMA5_QM_ARB_BASE_LO 0x5A8B54
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#define mmDMA5_QM_ARB_BASE_HI 0x5A8B58
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#define mmDMA5_QM_ARB_STATE_STS 0x5A8B80
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#define mmDMA5_QM_ARB_CHOISE_FULLNESS_STS 0x5A8B84
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#define mmDMA5_QM_ARB_MSG_STS 0x5A8B88
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#define mmDMA5_QM_ARB_SLV_CHOISE_Q_HEAD 0x5A8B8C
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#define mmDMA5_QM_ARB_ERR_CAUSE 0x5A8B9C
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#define mmDMA5_QM_ARB_ERR_MSG_EN 0x5A8BA0
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#define mmDMA5_QM_ARB_ERR_STS_DRP 0x5A8BA8
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#define mmDMA5_QM_ARB_MST_CRED_STS_0 0x5A8BB0
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#define mmDMA5_QM_ARB_MST_CRED_STS_1 0x5A8BB4
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#define mmDMA5_QM_ARB_MST_CRED_STS_2 0x5A8BB8
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#define mmDMA5_QM_ARB_MST_CRED_STS_3 0x5A8BBC
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#define mmDMA5_QM_ARB_MST_CRED_STS_4 0x5A8BC0
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#define mmDMA5_QM_ARB_MST_CRED_STS_5 0x5A8BC4
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#define mmDMA5_QM_ARB_MST_CRED_STS_6 0x5A8BC8
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#define mmDMA5_QM_ARB_MST_CRED_STS_7 0x5A8BCC
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#define mmDMA5_QM_ARB_MST_CRED_STS_8 0x5A8BD0
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#define mmDMA5_QM_ARB_MST_CRED_STS_9 0x5A8BD4
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#define mmDMA5_QM_ARB_MST_CRED_STS_10 0x5A8BD8
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#define mmDMA5_QM_ARB_MST_CRED_STS_11 0x5A8BDC
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#define mmDMA5_QM_ARB_MST_CRED_STS_12 0x5A8BE0
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#define mmDMA5_QM_ARB_MST_CRED_STS_13 0x5A8BE4
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#define mmDMA5_QM_ARB_MST_CRED_STS_14 0x5A8BE8
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#define mmDMA5_QM_ARB_MST_CRED_STS_15 0x5A8BEC
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#define mmDMA5_QM_ARB_MST_CRED_STS_16 0x5A8BF0
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#define mmDMA5_QM_ARB_MST_CRED_STS_17 0x5A8BF4
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#define mmDMA5_QM_ARB_MST_CRED_STS_18 0x5A8BF8
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#define mmDMA5_QM_ARB_MST_CRED_STS_19 0x5A8BFC
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#define mmDMA5_QM_ARB_MST_CRED_STS_20 0x5A8C00
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#define mmDMA5_QM_ARB_MST_CRED_STS_21 0x5A8C04
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#define mmDMA5_QM_ARB_MST_CRED_STS_22 0x5A8C08
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#define mmDMA5_QM_ARB_MST_CRED_STS_23 0x5A8C0C
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#define mmDMA5_QM_ARB_MST_CRED_STS_24 0x5A8C10
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#define mmDMA5_QM_ARB_MST_CRED_STS_25 0x5A8C14
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#define mmDMA5_QM_ARB_MST_CRED_STS_26 0x5A8C18
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#define mmDMA5_QM_ARB_MST_CRED_STS_27 0x5A8C1C
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#define mmDMA5_QM_ARB_MST_CRED_STS_28 0x5A8C20
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#define mmDMA5_QM_ARB_MST_CRED_STS_29 0x5A8C24
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#define mmDMA5_QM_ARB_MST_CRED_STS_30 0x5A8C28
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#define mmDMA5_QM_ARB_MST_CRED_STS_31 0x5A8C2C
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#define mmDMA5_QM_CGM_CFG 0x5A8C70
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#define mmDMA5_QM_CGM_STS 0x5A8C74
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#define mmDMA5_QM_CGM_CFG1 0x5A8C78
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#define mmDMA5_QM_LOCAL_RANGE_BASE 0x5A8C80
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#define mmDMA5_QM_LOCAL_RANGE_SIZE 0x5A8C84
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#define mmDMA5_QM_CSMR_STRICT_PRIO_CFG 0x5A8C90
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#define mmDMA5_QM_HBW_RD_RATE_LIM_CFG_1 0x5A8C94
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#define mmDMA5_QM_LBW_WR_RATE_LIM_CFG_0 0x5A8C98
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#define mmDMA5_QM_LBW_WR_RATE_LIM_CFG_1 0x5A8C9C
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#define mmDMA5_QM_HBW_RD_RATE_LIM_CFG_0 0x5A8CA0
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#define mmDMA5_QM_GLBL_AXCACHE 0x5A8CA4
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#define mmDMA5_QM_IND_GW_APB_CFG 0x5A8CB0
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#define mmDMA5_QM_IND_GW_APB_WDATA 0x5A8CB4
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#define mmDMA5_QM_IND_GW_APB_RDATA 0x5A8CB8
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#define mmDMA5_QM_IND_GW_APB_STATUS 0x5A8CBC
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#define mmDMA5_QM_GLBL_ERR_ADDR_LO 0x5A8CD0
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#define mmDMA5_QM_GLBL_ERR_ADDR_HI 0x5A8CD4
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#define mmDMA5_QM_GLBL_ERR_WDATA 0x5A8CD8
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#define mmDMA5_QM_GLBL_MEM_INIT_BUSY 0x5A8D00
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#endif /* ASIC_REG_DMA5_QM_REGS_H_ */
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