/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_DMA3_QM_REGS_H_
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#define ASIC_REG_DMA3_QM_REGS_H_
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/*
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*****************************************
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* DMA3_QM (Prototype: QMAN)
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*****************************************
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*/
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#define mmDMA3_QM_GLBL_CFG0 0x568000
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#define mmDMA3_QM_GLBL_CFG1 0x568004
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#define mmDMA3_QM_GLBL_PROT 0x568008
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#define mmDMA3_QM_GLBL_ERR_CFG 0x56800C
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#define mmDMA3_QM_GLBL_SECURE_PROPS_0 0x568010
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#define mmDMA3_QM_GLBL_SECURE_PROPS_1 0x568014
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#define mmDMA3_QM_GLBL_SECURE_PROPS_2 0x568018
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#define mmDMA3_QM_GLBL_SECURE_PROPS_3 0x56801C
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#define mmDMA3_QM_GLBL_SECURE_PROPS_4 0x568020
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#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_0 0x568024
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#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_1 0x568028
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#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_2 0x56802C
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#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_3 0x568030
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#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_4 0x568034
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#define mmDMA3_QM_GLBL_STS0 0x568038
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#define mmDMA3_QM_GLBL_STS1_0 0x568040
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#define mmDMA3_QM_GLBL_STS1_1 0x568044
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#define mmDMA3_QM_GLBL_STS1_2 0x568048
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#define mmDMA3_QM_GLBL_STS1_3 0x56804C
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#define mmDMA3_QM_GLBL_STS1_4 0x568050
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#define mmDMA3_QM_GLBL_MSG_EN_0 0x568054
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#define mmDMA3_QM_GLBL_MSG_EN_1 0x568058
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#define mmDMA3_QM_GLBL_MSG_EN_2 0x56805C
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#define mmDMA3_QM_GLBL_MSG_EN_3 0x568060
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#define mmDMA3_QM_GLBL_MSG_EN_4 0x568068
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#define mmDMA3_QM_PQ_BASE_LO_0 0x568070
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#define mmDMA3_QM_PQ_BASE_LO_1 0x568074
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#define mmDMA3_QM_PQ_BASE_LO_2 0x568078
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#define mmDMA3_QM_PQ_BASE_LO_3 0x56807C
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#define mmDMA3_QM_PQ_BASE_HI_0 0x568080
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#define mmDMA3_QM_PQ_BASE_HI_1 0x568084
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#define mmDMA3_QM_PQ_BASE_HI_2 0x568088
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#define mmDMA3_QM_PQ_BASE_HI_3 0x56808C
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#define mmDMA3_QM_PQ_SIZE_0 0x568090
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#define mmDMA3_QM_PQ_SIZE_1 0x568094
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#define mmDMA3_QM_PQ_SIZE_2 0x568098
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#define mmDMA3_QM_PQ_SIZE_3 0x56809C
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#define mmDMA3_QM_PQ_PI_0 0x5680A0
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#define mmDMA3_QM_PQ_PI_1 0x5680A4
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#define mmDMA3_QM_PQ_PI_2 0x5680A8
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#define mmDMA3_QM_PQ_PI_3 0x5680AC
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#define mmDMA3_QM_PQ_CI_0 0x5680B0
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#define mmDMA3_QM_PQ_CI_1 0x5680B4
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#define mmDMA3_QM_PQ_CI_2 0x5680B8
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#define mmDMA3_QM_PQ_CI_3 0x5680BC
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#define mmDMA3_QM_PQ_CFG0_0 0x5680C0
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#define mmDMA3_QM_PQ_CFG0_1 0x5680C4
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#define mmDMA3_QM_PQ_CFG0_2 0x5680C8
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#define mmDMA3_QM_PQ_CFG0_3 0x5680CC
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#define mmDMA3_QM_PQ_CFG1_0 0x5680D0
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#define mmDMA3_QM_PQ_CFG1_1 0x5680D4
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#define mmDMA3_QM_PQ_CFG1_2 0x5680D8
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#define mmDMA3_QM_PQ_CFG1_3 0x5680DC
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#define mmDMA3_QM_PQ_ARUSER_31_11_0 0x5680E0
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#define mmDMA3_QM_PQ_ARUSER_31_11_1 0x5680E4
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#define mmDMA3_QM_PQ_ARUSER_31_11_2 0x5680E8
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#define mmDMA3_QM_PQ_ARUSER_31_11_3 0x5680EC
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#define mmDMA3_QM_PQ_STS0_0 0x5680F0
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#define mmDMA3_QM_PQ_STS0_1 0x5680F4
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#define mmDMA3_QM_PQ_STS0_2 0x5680F8
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#define mmDMA3_QM_PQ_STS0_3 0x5680FC
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#define mmDMA3_QM_PQ_STS1_0 0x568100
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#define mmDMA3_QM_PQ_STS1_1 0x568104
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#define mmDMA3_QM_PQ_STS1_2 0x568108
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#define mmDMA3_QM_PQ_STS1_3 0x56810C
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#define mmDMA3_QM_CQ_CFG0_0 0x568110
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#define mmDMA3_QM_CQ_CFG0_1 0x568114
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#define mmDMA3_QM_CQ_CFG0_2 0x568118
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#define mmDMA3_QM_CQ_CFG0_3 0x56811C
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#define mmDMA3_QM_CQ_CFG0_4 0x568120
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#define mmDMA3_QM_CQ_CFG1_0 0x568124
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#define mmDMA3_QM_CQ_CFG1_1 0x568128
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#define mmDMA3_QM_CQ_CFG1_2 0x56812C
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#define mmDMA3_QM_CQ_CFG1_3 0x568130
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#define mmDMA3_QM_CQ_CFG1_4 0x568134
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#define mmDMA3_QM_CQ_ARUSER_31_11_0 0x568138
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#define mmDMA3_QM_CQ_ARUSER_31_11_1 0x56813C
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#define mmDMA3_QM_CQ_ARUSER_31_11_2 0x568140
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#define mmDMA3_QM_CQ_ARUSER_31_11_3 0x568144
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#define mmDMA3_QM_CQ_ARUSER_31_11_4 0x568148
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#define mmDMA3_QM_CQ_STS0_0 0x56814C
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#define mmDMA3_QM_CQ_STS0_1 0x568150
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#define mmDMA3_QM_CQ_STS0_2 0x568154
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#define mmDMA3_QM_CQ_STS0_3 0x568158
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#define mmDMA3_QM_CQ_STS0_4 0x56815C
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#define mmDMA3_QM_CQ_STS1_0 0x568160
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#define mmDMA3_QM_CQ_STS1_1 0x568164
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#define mmDMA3_QM_CQ_STS1_2 0x568168
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#define mmDMA3_QM_CQ_STS1_3 0x56816C
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#define mmDMA3_QM_CQ_STS1_4 0x568170
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#define mmDMA3_QM_CQ_PTR_LO_0 0x568174
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#define mmDMA3_QM_CQ_PTR_HI_0 0x568178
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#define mmDMA3_QM_CQ_TSIZE_0 0x56817C
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#define mmDMA3_QM_CQ_CTL_0 0x568180
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#define mmDMA3_QM_CQ_PTR_LO_1 0x568184
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#define mmDMA3_QM_CQ_PTR_HI_1 0x568188
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#define mmDMA3_QM_CQ_TSIZE_1 0x56818C
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#define mmDMA3_QM_CQ_CTL_1 0x568190
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#define mmDMA3_QM_CQ_PTR_LO_2 0x568194
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#define mmDMA3_QM_CQ_PTR_HI_2 0x568198
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#define mmDMA3_QM_CQ_TSIZE_2 0x56819C
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#define mmDMA3_QM_CQ_CTL_2 0x5681A0
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#define mmDMA3_QM_CQ_PTR_LO_3 0x5681A4
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#define mmDMA3_QM_CQ_PTR_HI_3 0x5681A8
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#define mmDMA3_QM_CQ_TSIZE_3 0x5681AC
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#define mmDMA3_QM_CQ_CTL_3 0x5681B0
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#define mmDMA3_QM_CQ_PTR_LO_4 0x5681B4
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#define mmDMA3_QM_CQ_PTR_HI_4 0x5681B8
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#define mmDMA3_QM_CQ_TSIZE_4 0x5681BC
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#define mmDMA3_QM_CQ_CTL_4 0x5681C0
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#define mmDMA3_QM_CQ_PTR_LO_STS_0 0x5681C4
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#define mmDMA3_QM_CQ_PTR_LO_STS_1 0x5681C8
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#define mmDMA3_QM_CQ_PTR_LO_STS_2 0x5681CC
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#define mmDMA3_QM_CQ_PTR_LO_STS_3 0x5681D0
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#define mmDMA3_QM_CQ_PTR_LO_STS_4 0x5681D4
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#define mmDMA3_QM_CQ_PTR_HI_STS_0 0x5681D8
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#define mmDMA3_QM_CQ_PTR_HI_STS_1 0x5681DC
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#define mmDMA3_QM_CQ_PTR_HI_STS_2 0x5681E0
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#define mmDMA3_QM_CQ_PTR_HI_STS_3 0x5681E4
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#define mmDMA3_QM_CQ_PTR_HI_STS_4 0x5681E8
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#define mmDMA3_QM_CQ_TSIZE_STS_0 0x5681EC
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#define mmDMA3_QM_CQ_TSIZE_STS_1 0x5681F0
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#define mmDMA3_QM_CQ_TSIZE_STS_2 0x5681F4
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#define mmDMA3_QM_CQ_TSIZE_STS_3 0x5681F8
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#define mmDMA3_QM_CQ_TSIZE_STS_4 0x5681FC
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#define mmDMA3_QM_CQ_CTL_STS_0 0x568200
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#define mmDMA3_QM_CQ_CTL_STS_1 0x568204
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#define mmDMA3_QM_CQ_CTL_STS_2 0x568208
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#define mmDMA3_QM_CQ_CTL_STS_3 0x56820C
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#define mmDMA3_QM_CQ_CTL_STS_4 0x568210
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#define mmDMA3_QM_CQ_IFIFO_CNT_0 0x568214
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#define mmDMA3_QM_CQ_IFIFO_CNT_1 0x568218
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#define mmDMA3_QM_CQ_IFIFO_CNT_2 0x56821C
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#define mmDMA3_QM_CQ_IFIFO_CNT_3 0x568220
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#define mmDMA3_QM_CQ_IFIFO_CNT_4 0x568224
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#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_0 0x568228
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#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_1 0x56822C
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#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_2 0x568230
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#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_3 0x568234
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#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_4 0x568238
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#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_0 0x56823C
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#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_1 0x568240
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#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_2 0x568244
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#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_3 0x568248
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#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_4 0x56824C
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#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_0 0x568250
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#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_1 0x568254
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#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_2 0x568258
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#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_3 0x56825C
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#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_4 0x568260
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#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_0 0x568264
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#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_1 0x568268
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#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_2 0x56826C
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#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_3 0x568270
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#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_4 0x568274
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#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_0 0x568278
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#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_1 0x56827C
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#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_2 0x568280
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#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_3 0x568284
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#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_4 0x568288
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#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_0 0x56828C
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#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_1 0x568290
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#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_2 0x568294
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#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_3 0x568298
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#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_4 0x56829C
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#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_0 0x5682A0
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#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_1 0x5682A4
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#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_2 0x5682A8
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#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_3 0x5682AC
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#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_4 0x5682B0
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#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_0 0x5682B4
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#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_1 0x5682B8
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#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_2 0x5682BC
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#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_3 0x5682C0
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#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_4 0x5682C4
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#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_0 0x5682C8
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#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_1 0x5682CC
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#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_2 0x5682D0
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#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_3 0x5682D4
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#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_4 0x5682D8
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#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5682E0
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#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5682E4
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#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5682E8
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#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5682EC
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#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5682F0
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#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5682F4
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#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5682F8
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#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5682FC
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#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x568300
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#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x568304
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#define mmDMA3_QM_CP_FENCE0_RDATA_0 0x568308
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#define mmDMA3_QM_CP_FENCE0_RDATA_1 0x56830C
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#define mmDMA3_QM_CP_FENCE0_RDATA_2 0x568310
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#define mmDMA3_QM_CP_FENCE0_RDATA_3 0x568314
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#define mmDMA3_QM_CP_FENCE0_RDATA_4 0x568318
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#define mmDMA3_QM_CP_FENCE1_RDATA_0 0x56831C
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#define mmDMA3_QM_CP_FENCE1_RDATA_1 0x568320
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#define mmDMA3_QM_CP_FENCE1_RDATA_2 0x568324
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#define mmDMA3_QM_CP_FENCE1_RDATA_3 0x568328
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#define mmDMA3_QM_CP_FENCE1_RDATA_4 0x56832C
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#define mmDMA3_QM_CP_FENCE2_RDATA_0 0x568330
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#define mmDMA3_QM_CP_FENCE2_RDATA_1 0x568334
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#define mmDMA3_QM_CP_FENCE2_RDATA_2 0x568338
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#define mmDMA3_QM_CP_FENCE2_RDATA_3 0x56833C
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#define mmDMA3_QM_CP_FENCE2_RDATA_4 0x568340
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#define mmDMA3_QM_CP_FENCE3_RDATA_0 0x568344
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#define mmDMA3_QM_CP_FENCE3_RDATA_1 0x568348
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#define mmDMA3_QM_CP_FENCE3_RDATA_2 0x56834C
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#define mmDMA3_QM_CP_FENCE3_RDATA_3 0x568350
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#define mmDMA3_QM_CP_FENCE3_RDATA_4 0x568354
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#define mmDMA3_QM_CP_FENCE0_CNT_0 0x568358
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#define mmDMA3_QM_CP_FENCE0_CNT_1 0x56835C
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#define mmDMA3_QM_CP_FENCE0_CNT_2 0x568360
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#define mmDMA3_QM_CP_FENCE0_CNT_3 0x568364
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#define mmDMA3_QM_CP_FENCE0_CNT_4 0x568368
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#define mmDMA3_QM_CP_FENCE1_CNT_0 0x56836C
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#define mmDMA3_QM_CP_FENCE1_CNT_1 0x568370
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#define mmDMA3_QM_CP_FENCE1_CNT_2 0x568374
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#define mmDMA3_QM_CP_FENCE1_CNT_3 0x568378
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#define mmDMA3_QM_CP_FENCE1_CNT_4 0x56837C
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#define mmDMA3_QM_CP_FENCE2_CNT_0 0x568380
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#define mmDMA3_QM_CP_FENCE2_CNT_1 0x568384
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#define mmDMA3_QM_CP_FENCE2_CNT_2 0x568388
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#define mmDMA3_QM_CP_FENCE2_CNT_3 0x56838C
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#define mmDMA3_QM_CP_FENCE2_CNT_4 0x568390
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#define mmDMA3_QM_CP_FENCE3_CNT_0 0x568394
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#define mmDMA3_QM_CP_FENCE3_CNT_1 0x568398
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#define mmDMA3_QM_CP_FENCE3_CNT_2 0x56839C
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#define mmDMA3_QM_CP_FENCE3_CNT_3 0x5683A0
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#define mmDMA3_QM_CP_FENCE3_CNT_4 0x5683A4
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#define mmDMA3_QM_CP_STS_0 0x5683A8
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#define mmDMA3_QM_CP_STS_1 0x5683AC
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#define mmDMA3_QM_CP_STS_2 0x5683B0
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#define mmDMA3_QM_CP_STS_3 0x5683B4
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#define mmDMA3_QM_CP_STS_4 0x5683B8
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#define mmDMA3_QM_CP_CURRENT_INST_LO_0 0x5683BC
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#define mmDMA3_QM_CP_CURRENT_INST_LO_1 0x5683C0
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#define mmDMA3_QM_CP_CURRENT_INST_LO_2 0x5683C4
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#define mmDMA3_QM_CP_CURRENT_INST_LO_3 0x5683C8
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#define mmDMA3_QM_CP_CURRENT_INST_LO_4 0x5683CC
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#define mmDMA3_QM_CP_CURRENT_INST_HI_0 0x5683D0
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#define mmDMA3_QM_CP_CURRENT_INST_HI_1 0x5683D4
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#define mmDMA3_QM_CP_CURRENT_INST_HI_2 0x5683D8
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#define mmDMA3_QM_CP_CURRENT_INST_HI_3 0x5683DC
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#define mmDMA3_QM_CP_CURRENT_INST_HI_4 0x5683E0
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#define mmDMA3_QM_CP_BARRIER_CFG_0 0x5683F4
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#define mmDMA3_QM_CP_BARRIER_CFG_1 0x5683F8
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#define mmDMA3_QM_CP_BARRIER_CFG_2 0x5683FC
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#define mmDMA3_QM_CP_BARRIER_CFG_3 0x568400
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#define mmDMA3_QM_CP_BARRIER_CFG_4 0x568404
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#define mmDMA3_QM_CP_DBG_0_0 0x568408
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#define mmDMA3_QM_CP_DBG_0_1 0x56840C
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#define mmDMA3_QM_CP_DBG_0_2 0x568410
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#define mmDMA3_QM_CP_DBG_0_3 0x568414
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#define mmDMA3_QM_CP_DBG_0_4 0x568418
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#define mmDMA3_QM_CP_ARUSER_31_11_0 0x56841C
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#define mmDMA3_QM_CP_ARUSER_31_11_1 0x568420
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#define mmDMA3_QM_CP_ARUSER_31_11_2 0x568424
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#define mmDMA3_QM_CP_ARUSER_31_11_3 0x568428
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#define mmDMA3_QM_CP_ARUSER_31_11_4 0x56842C
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#define mmDMA3_QM_CP_AWUSER_31_11_0 0x568430
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#define mmDMA3_QM_CP_AWUSER_31_11_1 0x568434
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#define mmDMA3_QM_CP_AWUSER_31_11_2 0x568438
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#define mmDMA3_QM_CP_AWUSER_31_11_3 0x56843C
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#define mmDMA3_QM_CP_AWUSER_31_11_4 0x568440
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#define mmDMA3_QM_ARB_CFG_0 0x568A00
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#define mmDMA3_QM_ARB_CHOISE_Q_PUSH 0x568A04
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#define mmDMA3_QM_ARB_WRR_WEIGHT_0 0x568A08
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#define mmDMA3_QM_ARB_WRR_WEIGHT_1 0x568A0C
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#define mmDMA3_QM_ARB_WRR_WEIGHT_2 0x568A10
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#define mmDMA3_QM_ARB_WRR_WEIGHT_3 0x568A14
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#define mmDMA3_QM_ARB_CFG_1 0x568A18
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_0 0x568A20
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_1 0x568A24
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_2 0x568A28
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_3 0x568A2C
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_4 0x568A30
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_5 0x568A34
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_6 0x568A38
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_7 0x568A3C
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_8 0x568A40
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_9 0x568A44
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_10 0x568A48
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_11 0x568A4C
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_12 0x568A50
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_13 0x568A54
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_14 0x568A58
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_15 0x568A5C
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_16 0x568A60
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_17 0x568A64
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_18 0x568A68
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_19 0x568A6C
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_20 0x568A70
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_21 0x568A74
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_22 0x568A78
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_23 0x568A7C
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_24 0x568A80
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_25 0x568A84
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_26 0x568A88
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_27 0x568A8C
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_28 0x568A90
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_29 0x568A94
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_30 0x568A98
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#define mmDMA3_QM_ARB_MST_AVAIL_CRED_31 0x568A9C
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#define mmDMA3_QM_ARB_MST_CRED_INC 0x568AA0
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x568AA4
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x568AA8
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x568AAC
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x568AB0
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x568AB4
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x568AB8
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x568ABC
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x568AC0
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x568AC4
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x568AC8
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x568ACC
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x568AD0
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x568AD4
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x568AD8
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x568ADC
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x568AE0
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x568AE4
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x568AE8
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x568AEC
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x568AF0
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x568AF4
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x568AF8
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x568AFC
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x568B00
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x568B04
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x568B08
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x568B0C
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x568B10
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x568B14
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x568B18
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x568B1C
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#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x568B20
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#define mmDMA3_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x568B28
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#define mmDMA3_QM_ARB_MST_SLAVE_EN 0x568B2C
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#define mmDMA3_QM_ARB_MST_QUIET_PER 0x568B34
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#define mmDMA3_QM_ARB_SLV_CHOISE_WDT 0x568B38
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#define mmDMA3_QM_ARB_SLV_ID 0x568B3C
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#define mmDMA3_QM_ARB_MSG_MAX_INFLIGHT 0x568B44
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#define mmDMA3_QM_ARB_MSG_AWUSER_31_11 0x568B48
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#define mmDMA3_QM_ARB_MSG_AWUSER_SEC_PROP 0x568B4C
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#define mmDMA3_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x568B50
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#define mmDMA3_QM_ARB_BASE_LO 0x568B54
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#define mmDMA3_QM_ARB_BASE_HI 0x568B58
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#define mmDMA3_QM_ARB_STATE_STS 0x568B80
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#define mmDMA3_QM_ARB_CHOISE_FULLNESS_STS 0x568B84
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#define mmDMA3_QM_ARB_MSG_STS 0x568B88
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#define mmDMA3_QM_ARB_SLV_CHOISE_Q_HEAD 0x568B8C
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#define mmDMA3_QM_ARB_ERR_CAUSE 0x568B9C
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#define mmDMA3_QM_ARB_ERR_MSG_EN 0x568BA0
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#define mmDMA3_QM_ARB_ERR_STS_DRP 0x568BA8
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#define mmDMA3_QM_ARB_MST_CRED_STS_0 0x568BB0
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#define mmDMA3_QM_ARB_MST_CRED_STS_1 0x568BB4
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#define mmDMA3_QM_ARB_MST_CRED_STS_2 0x568BB8
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#define mmDMA3_QM_ARB_MST_CRED_STS_3 0x568BBC
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#define mmDMA3_QM_ARB_MST_CRED_STS_4 0x568BC0
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#define mmDMA3_QM_ARB_MST_CRED_STS_5 0x568BC4
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#define mmDMA3_QM_ARB_MST_CRED_STS_6 0x568BC8
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#define mmDMA3_QM_ARB_MST_CRED_STS_7 0x568BCC
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#define mmDMA3_QM_ARB_MST_CRED_STS_8 0x568BD0
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#define mmDMA3_QM_ARB_MST_CRED_STS_9 0x568BD4
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#define mmDMA3_QM_ARB_MST_CRED_STS_10 0x568BD8
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#define mmDMA3_QM_ARB_MST_CRED_STS_11 0x568BDC
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#define mmDMA3_QM_ARB_MST_CRED_STS_12 0x568BE0
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#define mmDMA3_QM_ARB_MST_CRED_STS_13 0x568BE4
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#define mmDMA3_QM_ARB_MST_CRED_STS_14 0x568BE8
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#define mmDMA3_QM_ARB_MST_CRED_STS_15 0x568BEC
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#define mmDMA3_QM_ARB_MST_CRED_STS_16 0x568BF0
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#define mmDMA3_QM_ARB_MST_CRED_STS_17 0x568BF4
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#define mmDMA3_QM_ARB_MST_CRED_STS_18 0x568BF8
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#define mmDMA3_QM_ARB_MST_CRED_STS_19 0x568BFC
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#define mmDMA3_QM_ARB_MST_CRED_STS_20 0x568C00
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#define mmDMA3_QM_ARB_MST_CRED_STS_21 0x568C04
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#define mmDMA3_QM_ARB_MST_CRED_STS_22 0x568C08
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#define mmDMA3_QM_ARB_MST_CRED_STS_23 0x568C0C
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#define mmDMA3_QM_ARB_MST_CRED_STS_24 0x568C10
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#define mmDMA3_QM_ARB_MST_CRED_STS_25 0x568C14
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#define mmDMA3_QM_ARB_MST_CRED_STS_26 0x568C18
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#define mmDMA3_QM_ARB_MST_CRED_STS_27 0x568C1C
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#define mmDMA3_QM_ARB_MST_CRED_STS_28 0x568C20
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#define mmDMA3_QM_ARB_MST_CRED_STS_29 0x568C24
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#define mmDMA3_QM_ARB_MST_CRED_STS_30 0x568C28
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#define mmDMA3_QM_ARB_MST_CRED_STS_31 0x568C2C
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#define mmDMA3_QM_CGM_CFG 0x568C70
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#define mmDMA3_QM_CGM_STS 0x568C74
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#define mmDMA3_QM_CGM_CFG1 0x568C78
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#define mmDMA3_QM_LOCAL_RANGE_BASE 0x568C80
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#define mmDMA3_QM_LOCAL_RANGE_SIZE 0x568C84
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#define mmDMA3_QM_CSMR_STRICT_PRIO_CFG 0x568C90
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#define mmDMA3_QM_HBW_RD_RATE_LIM_CFG_1 0x568C94
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#define mmDMA3_QM_LBW_WR_RATE_LIM_CFG_0 0x568C98
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#define mmDMA3_QM_LBW_WR_RATE_LIM_CFG_1 0x568C9C
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#define mmDMA3_QM_HBW_RD_RATE_LIM_CFG_0 0x568CA0
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#define mmDMA3_QM_GLBL_AXCACHE 0x568CA4
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#define mmDMA3_QM_IND_GW_APB_CFG 0x568CB0
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#define mmDMA3_QM_IND_GW_APB_WDATA 0x568CB4
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#define mmDMA3_QM_IND_GW_APB_RDATA 0x568CB8
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#define mmDMA3_QM_IND_GW_APB_STATUS 0x568CBC
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#define mmDMA3_QM_GLBL_ERR_ADDR_LO 0x568CD0
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#define mmDMA3_QM_GLBL_ERR_ADDR_HI 0x568CD4
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#define mmDMA3_QM_GLBL_ERR_WDATA 0x568CD8
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#define mmDMA3_QM_GLBL_MEM_INIT_BUSY 0x568D00
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#endif /* ASIC_REG_DMA3_QM_REGS_H_ */
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