/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_DMA0_QM_REGS_H_
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#define ASIC_REG_DMA0_QM_REGS_H_
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/*
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*****************************************
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* DMA0_QM (Prototype: QMAN)
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*****************************************
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*/
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#define mmDMA0_QM_GLBL_CFG0 0x508000
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#define mmDMA0_QM_GLBL_CFG1 0x508004
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#define mmDMA0_QM_GLBL_PROT 0x508008
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#define mmDMA0_QM_GLBL_ERR_CFG 0x50800C
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#define mmDMA0_QM_GLBL_SECURE_PROPS_0 0x508010
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#define mmDMA0_QM_GLBL_SECURE_PROPS_1 0x508014
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#define mmDMA0_QM_GLBL_SECURE_PROPS_2 0x508018
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#define mmDMA0_QM_GLBL_SECURE_PROPS_3 0x50801C
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#define mmDMA0_QM_GLBL_SECURE_PROPS_4 0x508020
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#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_0 0x508024
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#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_1 0x508028
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#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_2 0x50802C
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#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_3 0x508030
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#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_4 0x508034
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#define mmDMA0_QM_GLBL_STS0 0x508038
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#define mmDMA0_QM_GLBL_STS1_0 0x508040
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#define mmDMA0_QM_GLBL_STS1_1 0x508044
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#define mmDMA0_QM_GLBL_STS1_2 0x508048
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#define mmDMA0_QM_GLBL_STS1_3 0x50804C
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#define mmDMA0_QM_GLBL_STS1_4 0x508050
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#define mmDMA0_QM_GLBL_MSG_EN_0 0x508054
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#define mmDMA0_QM_GLBL_MSG_EN_1 0x508058
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#define mmDMA0_QM_GLBL_MSG_EN_2 0x50805C
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#define mmDMA0_QM_GLBL_MSG_EN_3 0x508060
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#define mmDMA0_QM_GLBL_MSG_EN_4 0x508068
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#define mmDMA0_QM_PQ_BASE_LO_0 0x508070
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#define mmDMA0_QM_PQ_BASE_LO_1 0x508074
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#define mmDMA0_QM_PQ_BASE_LO_2 0x508078
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#define mmDMA0_QM_PQ_BASE_LO_3 0x50807C
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#define mmDMA0_QM_PQ_BASE_HI_0 0x508080
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#define mmDMA0_QM_PQ_BASE_HI_1 0x508084
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#define mmDMA0_QM_PQ_BASE_HI_2 0x508088
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#define mmDMA0_QM_PQ_BASE_HI_3 0x50808C
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#define mmDMA0_QM_PQ_SIZE_0 0x508090
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#define mmDMA0_QM_PQ_SIZE_1 0x508094
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#define mmDMA0_QM_PQ_SIZE_2 0x508098
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#define mmDMA0_QM_PQ_SIZE_3 0x50809C
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#define mmDMA0_QM_PQ_PI_0 0x5080A0
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#define mmDMA0_QM_PQ_PI_1 0x5080A4
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#define mmDMA0_QM_PQ_PI_2 0x5080A8
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#define mmDMA0_QM_PQ_PI_3 0x5080AC
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#define mmDMA0_QM_PQ_CI_0 0x5080B0
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#define mmDMA0_QM_PQ_CI_1 0x5080B4
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#define mmDMA0_QM_PQ_CI_2 0x5080B8
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#define mmDMA0_QM_PQ_CI_3 0x5080BC
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#define mmDMA0_QM_PQ_CFG0_0 0x5080C0
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#define mmDMA0_QM_PQ_CFG0_1 0x5080C4
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#define mmDMA0_QM_PQ_CFG0_2 0x5080C8
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#define mmDMA0_QM_PQ_CFG0_3 0x5080CC
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#define mmDMA0_QM_PQ_CFG1_0 0x5080D0
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#define mmDMA0_QM_PQ_CFG1_1 0x5080D4
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#define mmDMA0_QM_PQ_CFG1_2 0x5080D8
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#define mmDMA0_QM_PQ_CFG1_3 0x5080DC
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#define mmDMA0_QM_PQ_ARUSER_31_11_0 0x5080E0
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#define mmDMA0_QM_PQ_ARUSER_31_11_1 0x5080E4
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#define mmDMA0_QM_PQ_ARUSER_31_11_2 0x5080E8
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#define mmDMA0_QM_PQ_ARUSER_31_11_3 0x5080EC
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#define mmDMA0_QM_PQ_STS0_0 0x5080F0
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#define mmDMA0_QM_PQ_STS0_1 0x5080F4
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#define mmDMA0_QM_PQ_STS0_2 0x5080F8
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#define mmDMA0_QM_PQ_STS0_3 0x5080FC
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#define mmDMA0_QM_PQ_STS1_0 0x508100
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#define mmDMA0_QM_PQ_STS1_1 0x508104
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#define mmDMA0_QM_PQ_STS1_2 0x508108
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#define mmDMA0_QM_PQ_STS1_3 0x50810C
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#define mmDMA0_QM_CQ_CFG0_0 0x508110
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#define mmDMA0_QM_CQ_CFG0_1 0x508114
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#define mmDMA0_QM_CQ_CFG0_2 0x508118
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#define mmDMA0_QM_CQ_CFG0_3 0x50811C
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#define mmDMA0_QM_CQ_CFG0_4 0x508120
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#define mmDMA0_QM_CQ_CFG1_0 0x508124
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#define mmDMA0_QM_CQ_CFG1_1 0x508128
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#define mmDMA0_QM_CQ_CFG1_2 0x50812C
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#define mmDMA0_QM_CQ_CFG1_3 0x508130
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#define mmDMA0_QM_CQ_CFG1_4 0x508134
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#define mmDMA0_QM_CQ_ARUSER_31_11_0 0x508138
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#define mmDMA0_QM_CQ_ARUSER_31_11_1 0x50813C
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#define mmDMA0_QM_CQ_ARUSER_31_11_2 0x508140
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#define mmDMA0_QM_CQ_ARUSER_31_11_3 0x508144
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#define mmDMA0_QM_CQ_ARUSER_31_11_4 0x508148
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#define mmDMA0_QM_CQ_STS0_0 0x50814C
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#define mmDMA0_QM_CQ_STS0_1 0x508150
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#define mmDMA0_QM_CQ_STS0_2 0x508154
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#define mmDMA0_QM_CQ_STS0_3 0x508158
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#define mmDMA0_QM_CQ_STS0_4 0x50815C
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#define mmDMA0_QM_CQ_STS1_0 0x508160
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#define mmDMA0_QM_CQ_STS1_1 0x508164
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#define mmDMA0_QM_CQ_STS1_2 0x508168
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#define mmDMA0_QM_CQ_STS1_3 0x50816C
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#define mmDMA0_QM_CQ_STS1_4 0x508170
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#define mmDMA0_QM_CQ_PTR_LO_0 0x508174
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#define mmDMA0_QM_CQ_PTR_HI_0 0x508178
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#define mmDMA0_QM_CQ_TSIZE_0 0x50817C
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#define mmDMA0_QM_CQ_CTL_0 0x508180
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#define mmDMA0_QM_CQ_PTR_LO_1 0x508184
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#define mmDMA0_QM_CQ_PTR_HI_1 0x508188
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#define mmDMA0_QM_CQ_TSIZE_1 0x50818C
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#define mmDMA0_QM_CQ_CTL_1 0x508190
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#define mmDMA0_QM_CQ_PTR_LO_2 0x508194
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#define mmDMA0_QM_CQ_PTR_HI_2 0x508198
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#define mmDMA0_QM_CQ_TSIZE_2 0x50819C
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#define mmDMA0_QM_CQ_CTL_2 0x5081A0
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#define mmDMA0_QM_CQ_PTR_LO_3 0x5081A4
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#define mmDMA0_QM_CQ_PTR_HI_3 0x5081A8
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#define mmDMA0_QM_CQ_TSIZE_3 0x5081AC
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#define mmDMA0_QM_CQ_CTL_3 0x5081B0
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#define mmDMA0_QM_CQ_PTR_LO_4 0x5081B4
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#define mmDMA0_QM_CQ_PTR_HI_4 0x5081B8
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#define mmDMA0_QM_CQ_TSIZE_4 0x5081BC
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#define mmDMA0_QM_CQ_CTL_4 0x5081C0
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#define mmDMA0_QM_CQ_PTR_LO_STS_0 0x5081C4
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#define mmDMA0_QM_CQ_PTR_LO_STS_1 0x5081C8
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#define mmDMA0_QM_CQ_PTR_LO_STS_2 0x5081CC
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#define mmDMA0_QM_CQ_PTR_LO_STS_3 0x5081D0
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#define mmDMA0_QM_CQ_PTR_LO_STS_4 0x5081D4
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#define mmDMA0_QM_CQ_PTR_HI_STS_0 0x5081D8
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#define mmDMA0_QM_CQ_PTR_HI_STS_1 0x5081DC
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#define mmDMA0_QM_CQ_PTR_HI_STS_2 0x5081E0
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#define mmDMA0_QM_CQ_PTR_HI_STS_3 0x5081E4
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#define mmDMA0_QM_CQ_PTR_HI_STS_4 0x5081E8
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#define mmDMA0_QM_CQ_TSIZE_STS_0 0x5081EC
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#define mmDMA0_QM_CQ_TSIZE_STS_1 0x5081F0
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#define mmDMA0_QM_CQ_TSIZE_STS_2 0x5081F4
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#define mmDMA0_QM_CQ_TSIZE_STS_3 0x5081F8
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#define mmDMA0_QM_CQ_TSIZE_STS_4 0x5081FC
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#define mmDMA0_QM_CQ_CTL_STS_0 0x508200
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#define mmDMA0_QM_CQ_CTL_STS_1 0x508204
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#define mmDMA0_QM_CQ_CTL_STS_2 0x508208
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#define mmDMA0_QM_CQ_CTL_STS_3 0x50820C
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#define mmDMA0_QM_CQ_CTL_STS_4 0x508210
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#define mmDMA0_QM_CQ_IFIFO_CNT_0 0x508214
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#define mmDMA0_QM_CQ_IFIFO_CNT_1 0x508218
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#define mmDMA0_QM_CQ_IFIFO_CNT_2 0x50821C
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#define mmDMA0_QM_CQ_IFIFO_CNT_3 0x508220
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#define mmDMA0_QM_CQ_IFIFO_CNT_4 0x508224
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#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 0x508228
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#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_1 0x50822C
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#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_2 0x508230
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#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_3 0x508234
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#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_4 0x508238
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#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 0x50823C
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#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_1 0x508240
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#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_2 0x508244
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#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_3 0x508248
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#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_4 0x50824C
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#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 0x508250
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#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_1 0x508254
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#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_2 0x508258
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#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_3 0x50825C
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#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_4 0x508260
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#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 0x508264
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#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_1 0x508268
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#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_2 0x50826C
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#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_3 0x508270
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#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_4 0x508274
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#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 0x508278
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#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_1 0x50827C
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#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 0x508280
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#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_3 0x508284
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#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_4 0x508288
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#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 0x50828C
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#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_1 0x508290
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#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_2 0x508294
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#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_3 0x508298
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#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_4 0x50829C
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#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 0x5082A0
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#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_1 0x5082A4
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#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_2 0x5082A8
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#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_3 0x5082AC
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#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_4 0x5082B0
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#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 0x5082B4
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#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_1 0x5082B8
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#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_2 0x5082BC
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#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_3 0x5082C0
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#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_4 0x5082C4
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#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 0x5082C8
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#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_1 0x5082CC
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#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_2 0x5082D0
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#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_3 0x5082D4
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#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_4 0x5082D8
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#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5082E0
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#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5082E4
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#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5082E8
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#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5082EC
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#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5082F0
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#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5082F4
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#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5082F8
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#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5082FC
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#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x508300
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#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x508304
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#define mmDMA0_QM_CP_FENCE0_RDATA_0 0x508308
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#define mmDMA0_QM_CP_FENCE0_RDATA_1 0x50830C
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#define mmDMA0_QM_CP_FENCE0_RDATA_2 0x508310
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#define mmDMA0_QM_CP_FENCE0_RDATA_3 0x508314
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#define mmDMA0_QM_CP_FENCE0_RDATA_4 0x508318
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#define mmDMA0_QM_CP_FENCE1_RDATA_0 0x50831C
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#define mmDMA0_QM_CP_FENCE1_RDATA_1 0x508320
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#define mmDMA0_QM_CP_FENCE1_RDATA_2 0x508324
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#define mmDMA0_QM_CP_FENCE1_RDATA_3 0x508328
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#define mmDMA0_QM_CP_FENCE1_RDATA_4 0x50832C
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#define mmDMA0_QM_CP_FENCE2_RDATA_0 0x508330
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#define mmDMA0_QM_CP_FENCE2_RDATA_1 0x508334
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#define mmDMA0_QM_CP_FENCE2_RDATA_2 0x508338
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#define mmDMA0_QM_CP_FENCE2_RDATA_3 0x50833C
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#define mmDMA0_QM_CP_FENCE2_RDATA_4 0x508340
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#define mmDMA0_QM_CP_FENCE3_RDATA_0 0x508344
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#define mmDMA0_QM_CP_FENCE3_RDATA_1 0x508348
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#define mmDMA0_QM_CP_FENCE3_RDATA_2 0x50834C
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#define mmDMA0_QM_CP_FENCE3_RDATA_3 0x508350
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#define mmDMA0_QM_CP_FENCE3_RDATA_4 0x508354
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#define mmDMA0_QM_CP_FENCE0_CNT_0 0x508358
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#define mmDMA0_QM_CP_FENCE0_CNT_1 0x50835C
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#define mmDMA0_QM_CP_FENCE0_CNT_2 0x508360
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#define mmDMA0_QM_CP_FENCE0_CNT_3 0x508364
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#define mmDMA0_QM_CP_FENCE0_CNT_4 0x508368
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#define mmDMA0_QM_CP_FENCE1_CNT_0 0x50836C
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#define mmDMA0_QM_CP_FENCE1_CNT_1 0x508370
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#define mmDMA0_QM_CP_FENCE1_CNT_2 0x508374
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#define mmDMA0_QM_CP_FENCE1_CNT_3 0x508378
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#define mmDMA0_QM_CP_FENCE1_CNT_4 0x50837C
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#define mmDMA0_QM_CP_FENCE2_CNT_0 0x508380
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#define mmDMA0_QM_CP_FENCE2_CNT_1 0x508384
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#define mmDMA0_QM_CP_FENCE2_CNT_2 0x508388
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#define mmDMA0_QM_CP_FENCE2_CNT_3 0x50838C
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#define mmDMA0_QM_CP_FENCE2_CNT_4 0x508390
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#define mmDMA0_QM_CP_FENCE3_CNT_0 0x508394
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#define mmDMA0_QM_CP_FENCE3_CNT_1 0x508398
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#define mmDMA0_QM_CP_FENCE3_CNT_2 0x50839C
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#define mmDMA0_QM_CP_FENCE3_CNT_3 0x5083A0
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#define mmDMA0_QM_CP_FENCE3_CNT_4 0x5083A4
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#define mmDMA0_QM_CP_STS_0 0x5083A8
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#define mmDMA0_QM_CP_STS_1 0x5083AC
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#define mmDMA0_QM_CP_STS_2 0x5083B0
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#define mmDMA0_QM_CP_STS_3 0x5083B4
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#define mmDMA0_QM_CP_STS_4 0x5083B8
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#define mmDMA0_QM_CP_CURRENT_INST_LO_0 0x5083BC
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#define mmDMA0_QM_CP_CURRENT_INST_LO_1 0x5083C0
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#define mmDMA0_QM_CP_CURRENT_INST_LO_2 0x5083C4
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#define mmDMA0_QM_CP_CURRENT_INST_LO_3 0x5083C8
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#define mmDMA0_QM_CP_CURRENT_INST_LO_4 0x5083CC
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#define mmDMA0_QM_CP_CURRENT_INST_HI_0 0x5083D0
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#define mmDMA0_QM_CP_CURRENT_INST_HI_1 0x5083D4
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#define mmDMA0_QM_CP_CURRENT_INST_HI_2 0x5083D8
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#define mmDMA0_QM_CP_CURRENT_INST_HI_3 0x5083DC
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#define mmDMA0_QM_CP_CURRENT_INST_HI_4 0x5083E0
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#define mmDMA0_QM_CP_BARRIER_CFG_0 0x5083F4
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#define mmDMA0_QM_CP_BARRIER_CFG_1 0x5083F8
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#define mmDMA0_QM_CP_BARRIER_CFG_2 0x5083FC
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#define mmDMA0_QM_CP_BARRIER_CFG_3 0x508400
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#define mmDMA0_QM_CP_BARRIER_CFG_4 0x508404
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#define mmDMA0_QM_CP_DBG_0_0 0x508408
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#define mmDMA0_QM_CP_DBG_0_1 0x50840C
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#define mmDMA0_QM_CP_DBG_0_2 0x508410
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#define mmDMA0_QM_CP_DBG_0_3 0x508414
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#define mmDMA0_QM_CP_DBG_0_4 0x508418
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#define mmDMA0_QM_CP_ARUSER_31_11_0 0x50841C
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#define mmDMA0_QM_CP_ARUSER_31_11_1 0x508420
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#define mmDMA0_QM_CP_ARUSER_31_11_2 0x508424
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#define mmDMA0_QM_CP_ARUSER_31_11_3 0x508428
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#define mmDMA0_QM_CP_ARUSER_31_11_4 0x50842C
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#define mmDMA0_QM_CP_AWUSER_31_11_0 0x508430
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#define mmDMA0_QM_CP_AWUSER_31_11_1 0x508434
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#define mmDMA0_QM_CP_AWUSER_31_11_2 0x508438
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#define mmDMA0_QM_CP_AWUSER_31_11_3 0x50843C
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#define mmDMA0_QM_CP_AWUSER_31_11_4 0x508440
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#define mmDMA0_QM_ARB_CFG_0 0x508A00
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#define mmDMA0_QM_ARB_CHOISE_Q_PUSH 0x508A04
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#define mmDMA0_QM_ARB_WRR_WEIGHT_0 0x508A08
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#define mmDMA0_QM_ARB_WRR_WEIGHT_1 0x508A0C
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#define mmDMA0_QM_ARB_WRR_WEIGHT_2 0x508A10
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#define mmDMA0_QM_ARB_WRR_WEIGHT_3 0x508A14
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#define mmDMA0_QM_ARB_CFG_1 0x508A18
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_0 0x508A20
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_1 0x508A24
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_2 0x508A28
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_3 0x508A2C
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_4 0x508A30
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_5 0x508A34
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_6 0x508A38
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_7 0x508A3C
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_8 0x508A40
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_9 0x508A44
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_10 0x508A48
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_11 0x508A4C
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_12 0x508A50
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_13 0x508A54
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_14 0x508A58
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_15 0x508A5C
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_16 0x508A60
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_17 0x508A64
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_18 0x508A68
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_19 0x508A6C
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_20 0x508A70
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_21 0x508A74
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_22 0x508A78
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_23 0x508A7C
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_24 0x508A80
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_25 0x508A84
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_26 0x508A88
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_27 0x508A8C
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_28 0x508A90
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_29 0x508A94
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_30 0x508A98
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#define mmDMA0_QM_ARB_MST_AVAIL_CRED_31 0x508A9C
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#define mmDMA0_QM_ARB_MST_CRED_INC 0x508AA0
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x508AA4
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x508AA8
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x508AAC
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x508AB0
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x508AB4
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x508AB8
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x508ABC
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x508AC0
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x508AC4
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x508AC8
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x508ACC
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x508AD0
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x508AD4
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x508AD8
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x508ADC
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x508AE0
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x508AE4
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x508AE8
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x508AEC
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x508AF0
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x508AF4
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x508AF8
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x508AFC
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x508B00
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x508B04
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x508B08
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x508B0C
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x508B10
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x508B14
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x508B18
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x508B1C
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#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x508B20
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#define mmDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x508B28
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#define mmDMA0_QM_ARB_MST_SLAVE_EN 0x508B2C
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#define mmDMA0_QM_ARB_MST_QUIET_PER 0x508B34
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#define mmDMA0_QM_ARB_SLV_CHOISE_WDT 0x508B38
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#define mmDMA0_QM_ARB_SLV_ID 0x508B3C
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#define mmDMA0_QM_ARB_MSG_MAX_INFLIGHT 0x508B44
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#define mmDMA0_QM_ARB_MSG_AWUSER_31_11 0x508B48
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#define mmDMA0_QM_ARB_MSG_AWUSER_SEC_PROP 0x508B4C
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#define mmDMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x508B50
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#define mmDMA0_QM_ARB_BASE_LO 0x508B54
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#define mmDMA0_QM_ARB_BASE_HI 0x508B58
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#define mmDMA0_QM_ARB_STATE_STS 0x508B80
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#define mmDMA0_QM_ARB_CHOISE_FULLNESS_STS 0x508B84
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#define mmDMA0_QM_ARB_MSG_STS 0x508B88
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#define mmDMA0_QM_ARB_SLV_CHOISE_Q_HEAD 0x508B8C
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#define mmDMA0_QM_ARB_ERR_CAUSE 0x508B9C
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#define mmDMA0_QM_ARB_ERR_MSG_EN 0x508BA0
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#define mmDMA0_QM_ARB_ERR_STS_DRP 0x508BA8
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#define mmDMA0_QM_ARB_MST_CRED_STS_0 0x508BB0
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#define mmDMA0_QM_ARB_MST_CRED_STS_1 0x508BB4
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#define mmDMA0_QM_ARB_MST_CRED_STS_2 0x508BB8
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#define mmDMA0_QM_ARB_MST_CRED_STS_3 0x508BBC
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#define mmDMA0_QM_ARB_MST_CRED_STS_4 0x508BC0
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#define mmDMA0_QM_ARB_MST_CRED_STS_5 0x508BC4
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#define mmDMA0_QM_ARB_MST_CRED_STS_6 0x508BC8
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#define mmDMA0_QM_ARB_MST_CRED_STS_7 0x508BCC
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#define mmDMA0_QM_ARB_MST_CRED_STS_8 0x508BD0
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#define mmDMA0_QM_ARB_MST_CRED_STS_9 0x508BD4
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#define mmDMA0_QM_ARB_MST_CRED_STS_10 0x508BD8
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#define mmDMA0_QM_ARB_MST_CRED_STS_11 0x508BDC
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#define mmDMA0_QM_ARB_MST_CRED_STS_12 0x508BE0
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#define mmDMA0_QM_ARB_MST_CRED_STS_13 0x508BE4
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#define mmDMA0_QM_ARB_MST_CRED_STS_14 0x508BE8
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#define mmDMA0_QM_ARB_MST_CRED_STS_15 0x508BEC
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#define mmDMA0_QM_ARB_MST_CRED_STS_16 0x508BF0
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#define mmDMA0_QM_ARB_MST_CRED_STS_17 0x508BF4
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#define mmDMA0_QM_ARB_MST_CRED_STS_18 0x508BF8
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#define mmDMA0_QM_ARB_MST_CRED_STS_19 0x508BFC
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#define mmDMA0_QM_ARB_MST_CRED_STS_20 0x508C00
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#define mmDMA0_QM_ARB_MST_CRED_STS_21 0x508C04
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#define mmDMA0_QM_ARB_MST_CRED_STS_22 0x508C08
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#define mmDMA0_QM_ARB_MST_CRED_STS_23 0x508C0C
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#define mmDMA0_QM_ARB_MST_CRED_STS_24 0x508C10
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#define mmDMA0_QM_ARB_MST_CRED_STS_25 0x508C14
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#define mmDMA0_QM_ARB_MST_CRED_STS_26 0x508C18
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#define mmDMA0_QM_ARB_MST_CRED_STS_27 0x508C1C
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#define mmDMA0_QM_ARB_MST_CRED_STS_28 0x508C20
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#define mmDMA0_QM_ARB_MST_CRED_STS_29 0x508C24
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#define mmDMA0_QM_ARB_MST_CRED_STS_30 0x508C28
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#define mmDMA0_QM_ARB_MST_CRED_STS_31 0x508C2C
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#define mmDMA0_QM_CGM_CFG 0x508C70
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#define mmDMA0_QM_CGM_STS 0x508C74
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#define mmDMA0_QM_CGM_CFG1 0x508C78
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#define mmDMA0_QM_LOCAL_RANGE_BASE 0x508C80
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#define mmDMA0_QM_LOCAL_RANGE_SIZE 0x508C84
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#define mmDMA0_QM_CSMR_STRICT_PRIO_CFG 0x508C90
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#define mmDMA0_QM_HBW_RD_RATE_LIM_CFG_1 0x508C94
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#define mmDMA0_QM_LBW_WR_RATE_LIM_CFG_0 0x508C98
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#define mmDMA0_QM_LBW_WR_RATE_LIM_CFG_1 0x508C9C
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#define mmDMA0_QM_HBW_RD_RATE_LIM_CFG_0 0x508CA0
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#define mmDMA0_QM_GLBL_AXCACHE 0x508CA4
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#define mmDMA0_QM_IND_GW_APB_CFG 0x508CB0
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#define mmDMA0_QM_IND_GW_APB_WDATA 0x508CB4
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#define mmDMA0_QM_IND_GW_APB_RDATA 0x508CB8
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#define mmDMA0_QM_IND_GW_APB_STATUS 0x508CBC
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#define mmDMA0_QM_GLBL_ERR_ADDR_LO 0x508CD0
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#define mmDMA0_QM_GLBL_ERR_ADDR_HI 0x508CD4
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#define mmDMA0_QM_GLBL_ERR_WDATA 0x508CD8
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#define mmDMA0_QM_GLBL_MEM_INIT_BUSY 0x508D00
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#endif /* ASIC_REG_DMA0_QM_REGS_H_ */
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