/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_CPU_IF_REGS_H_
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#define ASIC_REG_CPU_IF_REGS_H_
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/*
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*****************************************
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* CPU_IF (Prototype: CPU_IF)
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*****************************************
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*/
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#define mmCPU_IF_ARUSER_OVR 0x442104
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#define mmCPU_IF_ARUSER_OVR_EN 0x442108
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#define mmCPU_IF_AWUSER_OVR 0x44210C
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#define mmCPU_IF_AWUSER_OVR_EN 0x442110
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#define mmCPU_IF_AXCACHE_OVR 0x442114
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#define mmCPU_IF_LOCK_OVR 0x442118
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#define mmCPU_IF_PROT_OVR 0x44211C
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#define mmCPU_IF_MAX_OUTSTANDING 0x442120
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#define mmCPU_IF_EARLY_BRESP_EN 0x442124
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#define mmCPU_IF_FORCE_RSP_OK 0x442128
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#define mmCPU_IF_CPU_MSB_ADDR 0x44212C
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#define mmCPU_IF_AXI_SPLIT_INTR 0x442130
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#define mmCPU_IF_TOTAL_WR_CNT 0x442140
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#define mmCPU_IF_INFLIGHT_WR_CNT 0x442144
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#define mmCPU_IF_TOTAL_RD_CNT 0x442150
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#define mmCPU_IF_INFLIGHT_RD_CNT 0x442154
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#define mmCPU_IF_PF_PQ_PI 0x442200
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#define mmCPU_IF_PQ_BASE_ADDR_LOW 0x442204
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#define mmCPU_IF_PQ_BASE_ADDR_HIGH 0x442208
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#define mmCPU_IF_PQ_LENGTH 0x44220C
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#define mmCPU_IF_CQ_BASE_ADDR_LOW 0x442210
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#define mmCPU_IF_CQ_BASE_ADDR_HIGH 0x442214
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#define mmCPU_IF_CQ_LENGTH 0x442218
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#define mmCPU_IF_EQ_BASE_ADDR_LOW 0x442220
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#define mmCPU_IF_EQ_BASE_ADDR_HIGH 0x442224
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#define mmCPU_IF_EQ_LENGTH 0x442228
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#define mmCPU_IF_EQ_RD_OFFS 0x44222C
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#define mmCPU_IF_QUEUE_INIT 0x442230
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#define mmCPU_IF_TPC_SERR_INTR_STS 0x442300
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#define mmCPU_IF_TPC_SERR_INTR_CLR 0x442304
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#define mmCPU_IF_TPC_SERR_INTR_MASK 0x442308
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#define mmCPU_IF_TPC_DERR_INTR_STS 0x442310
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#define mmCPU_IF_TPC_DERR_INTR_CLR 0x442314
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#define mmCPU_IF_TPC_DERR_INTR_MASK 0x442318
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#define mmCPU_IF_DMA_SERR_INTR_STS 0x442320
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#define mmCPU_IF_DMA_SERR_INTR_CLR 0x442324
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#define mmCPU_IF_DMA_SERR_INTR_MASK 0x442328
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#define mmCPU_IF_DMA_DERR_INTR_STS 0x442330
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#define mmCPU_IF_DMA_DERR_INTR_CLR 0x442334
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#define mmCPU_IF_DMA_DERR_INTR_MASK 0x442338
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#define mmCPU_IF_SRAM_SERR_INTR_STS 0x442340
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#define mmCPU_IF_SRAM_SERR_INTR_CLR 0x442344
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#define mmCPU_IF_SRAM_SERR_INTR_MASK 0x442348
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#define mmCPU_IF_SRAM_DERR_INTR_STS 0x442350
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#define mmCPU_IF_SRAM_DERR_INTR_CLR 0x442354
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#define mmCPU_IF_SRAM_DERR_INTR_MASK 0x442358
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#define mmCPU_IF_NIC_SERR_INTR_STS 0x442360
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#define mmCPU_IF_NIC_SERR_INTR_CLR 0x442364
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#define mmCPU_IF_NIC_SERR_INTR_MASK 0x442368
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#define mmCPU_IF_NIC_DERR_INTR_STS 0x442370
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#define mmCPU_IF_NIC_DERR_INTR_CLR 0x442374
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#define mmCPU_IF_NIC_DERR_INTR_MASK 0x442378
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#define mmCPU_IF_DMA_IF_SERR_INTR_STS 0x442380
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#define mmCPU_IF_DMA_IF_SERR_INTR_CLR 0x442384
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#define mmCPU_IF_DMA_IF_SERR_INTR_MASK 0x442388
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#define mmCPU_IF_DMA_IF_DERR_INTR_STS 0x442390
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#define mmCPU_IF_DMA_IF_DERR_INTR_CLR 0x442394
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#define mmCPU_IF_DMA_IF_DERR_INTR_MASK 0x442398
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#define mmCPU_IF_HBM_SERR_INTR_STS 0x4423A0
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#define mmCPU_IF_HBM_SERR_INTR_CLR 0x4423A4
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#define mmCPU_IF_HBM_SERR_INTR_MASK 0x4423A8
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#define mmCPU_IF_HBM_DERR_INTR_STS 0x4423B0
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#define mmCPU_IF_HBM_DERR_INTR_CLR 0x4423B4
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#define mmCPU_IF_HBM_DERR_INTR_MASK 0x4423B8
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#define mmCPU_IF_PLL_SEI_INTR_STS 0x442400
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#define mmCPU_IF_PLL_SEI_INTR_CLR 0x442404
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#define mmCPU_IF_PLL_SEI_INTR_MASK 0x442408
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#define mmCPU_IF_NIC_SEI_INTR_STS 0x442410
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#define mmCPU_IF_NIC_SEI_INTR_CLR 0x442414
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#define mmCPU_IF_NIC_SEI_INTR_MASK 0x442418
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#define mmCPU_IF_DMA_SEI_INTR_STS 0x442420
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#define mmCPU_IF_DMA_SEI_INTR_CLR 0x442424
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#define mmCPU_IF_DMA_SEI_INTR_MASK 0x442428
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#define mmCPU_IF_DMA_IF_SEI_INTR_STS 0x442430
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#define mmCPU_IF_DMA_IF_SEI_INTR_CLR 0x442434
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#define mmCPU_IF_DMA_IF_SEI_INTR_MASK 0x442438
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#endif /* ASIC_REG_CPU_IF_REGS_H_ */
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