// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* maxim-max96772.c -- I2C register interface access for max96772 serdes chip
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*
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* Copyright (c) 2023-2028 Rockchip Electronics Co. Ltd.
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*
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* Author:
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*/
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#include "../core.h"
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#include "maxim-max96772.h"
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static const struct regmap_range max96772_readable_ranges[] = {
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regmap_reg_range(0x0000, 0x0800),
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regmap_reg_range(0x1700, 0x1700),
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regmap_reg_range(0x4100, 0x4100),
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regmap_reg_range(0x6230, 0x6230),
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regmap_reg_range(0xe75e, 0xe75e),
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regmap_reg_range(0xe776, 0xe7bf),
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};
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static const struct regmap_access_table max96772_readable_table = {
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.yes_ranges = max96772_readable_ranges,
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.n_yes_ranges = ARRAY_SIZE(max96772_readable_ranges),
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};
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static struct regmap_config max96772_regmap_config = {
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.name = "max96772",
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.reg_bits = 16,
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.val_bits = 8,
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.max_register = 0xffff,
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.rd_table = &max96772_readable_table,
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};
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struct config_desc {
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u16 reg;
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u8 mask;
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u8 val;
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};
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struct serdes_group_data {
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const struct config_desc *configs;
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int num_configs;
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};
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static int MAX96772_GPIO0_pins[] = {0};
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static int MAX96772_GPIO1_pins[] = {1};
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static int MAX96772_GPIO2_pins[] = {2};
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static int MAX96772_GPIO3_pins[] = {3};
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static int MAX96772_GPIO4_pins[] = {4};
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static int MAX96772_GPIO5_pins[] = {5};
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static int MAX96772_GPIO6_pins[] = {6};
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static int MAX96772_GPIO7_pins[] = {7};
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static int MAX96772_GPIO8_pins[] = {8};
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static int MAX96772_GPIO9_pins[] = {9};
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static int MAX96772_GPIO10_pins[] = {10};
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static int MAX96772_GPIO11_pins[] = {11};
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static int MAX96772_GPIO12_pins[] = {12};
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static int MAX96772_GPIO13_pins[] = {13};
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static int MAX96772_GPIO14_pins[] = {14};
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static int MAX96772_GPIO15_pins[] = {15};
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#define GROUP_DESC(nm) \
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{ \
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.name = #nm, \
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.pins = nm ## _pins, \
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.num_pins = ARRAY_SIZE(nm ## _pins), \
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}
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struct serdes_function_data {
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u8 gpio_out_dis:1;
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u8 gpio_tx_en:1;
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u8 gpio_rx_en:1;
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u8 gpio_in_level:1;
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u8 gpio_out_level:1;
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u8 gpio_tx_id;
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u8 gpio_rx_id;
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u16 mdelay;
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};
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static const char *serdes_gpio_groups[] = {
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"MAX96772_GPIO0", "MAX96772_GPIO1", "MAX96772_GPIO2", "MAX96772_GPIO3",
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"MAX96772_GPIO4", "MAX96772_GPIO5", "MAX96772_GPIO6", "MAX96772_GPIO7",
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"MAX96772_GPIO8", "MAX96772_GPIO9", "MAX96772_GPIO10", "MAX96772_GPIO11",
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"MAX96772_GPIO12", "MAX96772_GPIO13", "MAX96772_GPIO14", "MAX96772_GPIO15",
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};
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#define FUNCTION_DESC_GPIO_INPUT_BYPASS(id) \
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{ \
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.name = "SER_TO_DES_RXID"#id, \
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.group_names = serdes_gpio_groups, \
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.num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
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.data = (void *)(const struct serdes_function_data []) { \
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{ .gpio_rx_en = 1, .gpio_rx_id = id } \
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}, \
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} \
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#define FUNCTION_DESC_GPIO_OUTPUT_BYPASS(id) \
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{ \
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.name = "DES_TXID"#id"_TO_SER", \
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.group_names = serdes_gpio_groups, \
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.num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
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.data = (void *)(const struct serdes_function_data []) { \
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{ .gpio_out_dis = 1, .gpio_tx_en = 1, .gpio_tx_id = id } \
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}, \
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} \
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#define FUNCTION_DESC_GPIO_OUTPUT_LOW(id) \
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{ \
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.name = "DES_TXID"#id"_OUTPUT_LOW", \
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.group_names = serdes_gpio_groups, \
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.num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
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.data = (void *)(const struct serdes_function_data []) { \
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{ .gpio_out_dis = 0, .gpio_tx_en = 0, \
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.gpio_rx_en = 0, .gpio_out_level = 0, .gpio_tx_id = id } \
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}, \
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} \
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#define FUNCTION_DESC_GPIO_OUTPUT_HIGH(id) \
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{ \
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.name = "DES_TXID"#id"_OUTPUT_HIGH", \
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.group_names = serdes_gpio_groups, \
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.num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
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.data = (void *)(const struct serdes_function_data []) { \
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{ .gpio_out_dis = 0, .gpio_tx_en = 0, \
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.gpio_rx_en = 0, .gpio_out_level = 1, .gpio_tx_id = id } \
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}, \
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} \
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#define FUNCTION_DES_DELAY_MS(ms) \
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{ \
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.name = "DELAY_"#ms"MS", \
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.group_names = serdes_gpio_groups, \
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.num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
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.data = (void *)(const struct serdes_function_data []) { \
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{ .mdelay = ms, } \
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}, \
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} \
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static struct pinctrl_pin_desc max96772_pins_desc[] = {
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PINCTRL_PIN(MAXIM_MAX96772_GPIO0, "MAX96772_GPIO0"),
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PINCTRL_PIN(MAXIM_MAX96772_GPIO1, "MAX96772_GPIO1"),
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PINCTRL_PIN(MAXIM_MAX96772_GPIO2, "MAX96772_GPIO2"),
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PINCTRL_PIN(MAXIM_MAX96772_GPIO3, "MAX96772_GPIO3"),
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PINCTRL_PIN(MAXIM_MAX96772_GPIO4, "MAX96772_GPIO4"),
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PINCTRL_PIN(MAXIM_MAX96772_GPIO5, "MAX96772_GPIO5"),
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PINCTRL_PIN(MAXIM_MAX96772_GPIO6, "MAX96772_GPIO6"),
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PINCTRL_PIN(MAXIM_MAX96772_GPIO7, "MAX96772_GPIO7"),
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PINCTRL_PIN(MAXIM_MAX96772_GPIO8, "MAX96772_GPIO8"),
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PINCTRL_PIN(MAXIM_MAX96772_GPIO9, "MAX96772_GPIO9"),
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PINCTRL_PIN(MAXIM_MAX96772_GPIO10, "MAX96772_GPIO10"),
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PINCTRL_PIN(MAXIM_MAX96772_GPIO11, "MAX96772_GPIO11"),
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PINCTRL_PIN(MAXIM_MAX96772_GPIO12, "MAX96772_GPIO12"),
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PINCTRL_PIN(MAXIM_MAX96772_GPIO13, "MAX96772_GPIO13"),
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PINCTRL_PIN(MAXIM_MAX96772_GPIO14, "MAX96772_GPIO14"),
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PINCTRL_PIN(MAXIM_MAX96772_GPIO15, "MAX96772_GPIO15"),
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};
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static struct group_desc max96772_groups_desc[] = {
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GROUP_DESC(MAX96772_GPIO0),
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GROUP_DESC(MAX96772_GPIO1),
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GROUP_DESC(MAX96772_GPIO2),
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GROUP_DESC(MAX96772_GPIO3),
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GROUP_DESC(MAX96772_GPIO4),
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GROUP_DESC(MAX96772_GPIO5),
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GROUP_DESC(MAX96772_GPIO6),
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GROUP_DESC(MAX96772_GPIO7),
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GROUP_DESC(MAX96772_GPIO8),
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GROUP_DESC(MAX96772_GPIO9),
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GROUP_DESC(MAX96772_GPIO10),
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GROUP_DESC(MAX96772_GPIO11),
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GROUP_DESC(MAX96772_GPIO12),
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GROUP_DESC(MAX96772_GPIO13),
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GROUP_DESC(MAX96772_GPIO14),
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GROUP_DESC(MAX96772_GPIO15),
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};
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static struct function_desc max96772_functions_desc[] = {
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FUNCTION_DESC_GPIO_INPUT_BYPASS(0),
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FUNCTION_DESC_GPIO_INPUT_BYPASS(1),
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FUNCTION_DESC_GPIO_INPUT_BYPASS(2),
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FUNCTION_DESC_GPIO_INPUT_BYPASS(3),
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FUNCTION_DESC_GPIO_INPUT_BYPASS(4),
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FUNCTION_DESC_GPIO_INPUT_BYPASS(5),
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FUNCTION_DESC_GPIO_INPUT_BYPASS(6),
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FUNCTION_DESC_GPIO_INPUT_BYPASS(7),
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FUNCTION_DESC_GPIO_INPUT_BYPASS(8),
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FUNCTION_DESC_GPIO_INPUT_BYPASS(9),
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FUNCTION_DESC_GPIO_INPUT_BYPASS(10),
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FUNCTION_DESC_GPIO_INPUT_BYPASS(11),
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FUNCTION_DESC_GPIO_INPUT_BYPASS(12),
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FUNCTION_DESC_GPIO_INPUT_BYPASS(13),
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FUNCTION_DESC_GPIO_INPUT_BYPASS(14),
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FUNCTION_DESC_GPIO_INPUT_BYPASS(15),
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FUNCTION_DESC_GPIO_OUTPUT_BYPASS(0),
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FUNCTION_DESC_GPIO_OUTPUT_BYPASS(1),
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FUNCTION_DESC_GPIO_OUTPUT_BYPASS(2),
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FUNCTION_DESC_GPIO_OUTPUT_BYPASS(3),
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FUNCTION_DESC_GPIO_OUTPUT_BYPASS(4),
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FUNCTION_DESC_GPIO_OUTPUT_BYPASS(5),
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FUNCTION_DESC_GPIO_OUTPUT_BYPASS(6),
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FUNCTION_DESC_GPIO_OUTPUT_BYPASS(7),
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FUNCTION_DESC_GPIO_OUTPUT_BYPASS(8),
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FUNCTION_DESC_GPIO_OUTPUT_BYPASS(9),
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FUNCTION_DESC_GPIO_OUTPUT_BYPASS(10),
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FUNCTION_DESC_GPIO_OUTPUT_BYPASS(11),
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FUNCTION_DESC_GPIO_OUTPUT_BYPASS(12),
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FUNCTION_DESC_GPIO_OUTPUT_BYPASS(13),
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FUNCTION_DESC_GPIO_OUTPUT_BYPASS(14),
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FUNCTION_DESC_GPIO_OUTPUT_BYPASS(15),
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FUNCTION_DESC_GPIO_OUTPUT_LOW(0),
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FUNCTION_DESC_GPIO_OUTPUT_LOW(1),
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FUNCTION_DESC_GPIO_OUTPUT_LOW(2),
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FUNCTION_DESC_GPIO_OUTPUT_LOW(3),
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FUNCTION_DESC_GPIO_OUTPUT_LOW(4),
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FUNCTION_DESC_GPIO_OUTPUT_LOW(5),
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FUNCTION_DESC_GPIO_OUTPUT_LOW(6),
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FUNCTION_DESC_GPIO_OUTPUT_LOW(7),
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FUNCTION_DESC_GPIO_OUTPUT_LOW(8),
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FUNCTION_DESC_GPIO_OUTPUT_LOW(9),
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FUNCTION_DESC_GPIO_OUTPUT_LOW(10),
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FUNCTION_DESC_GPIO_OUTPUT_LOW(11),
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FUNCTION_DESC_GPIO_OUTPUT_LOW(12),
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FUNCTION_DESC_GPIO_OUTPUT_LOW(13),
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FUNCTION_DESC_GPIO_OUTPUT_LOW(14),
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FUNCTION_DESC_GPIO_OUTPUT_LOW(15),
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FUNCTION_DESC_GPIO_OUTPUT_HIGH(0),
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FUNCTION_DESC_GPIO_OUTPUT_HIGH(1),
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FUNCTION_DESC_GPIO_OUTPUT_HIGH(2),
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FUNCTION_DESC_GPIO_OUTPUT_HIGH(3),
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FUNCTION_DESC_GPIO_OUTPUT_HIGH(4),
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FUNCTION_DESC_GPIO_OUTPUT_HIGH(5),
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FUNCTION_DESC_GPIO_OUTPUT_HIGH(6),
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FUNCTION_DESC_GPIO_OUTPUT_HIGH(7),
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FUNCTION_DESC_GPIO_OUTPUT_HIGH(8),
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FUNCTION_DESC_GPIO_OUTPUT_HIGH(9),
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FUNCTION_DESC_GPIO_OUTPUT_HIGH(10),
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FUNCTION_DESC_GPIO_OUTPUT_HIGH(11),
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FUNCTION_DESC_GPIO_OUTPUT_HIGH(12),
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FUNCTION_DESC_GPIO_OUTPUT_HIGH(13),
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FUNCTION_DESC_GPIO_OUTPUT_HIGH(14),
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FUNCTION_DESC_GPIO_OUTPUT_HIGH(15),
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FUNCTION_DES_DELAY_MS(10),
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FUNCTION_DES_DELAY_MS(50),
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FUNCTION_DES_DELAY_MS(100),
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FUNCTION_DES_DELAY_MS(200),
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FUNCTION_DES_DELAY_MS(500),
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};
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static struct serdes_chip_pinctrl_info max96772_pinctrl_info = {
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.pins = max96772_pins_desc,
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.num_pins = ARRAY_SIZE(max96772_pins_desc),
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.groups = max96772_groups_desc,
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.num_groups = ARRAY_SIZE(max96772_groups_desc),
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.functions = max96772_functions_desc,
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.num_functions = ARRAY_SIZE(max96772_functions_desc),
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};
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static const struct reg_sequence max96772_clk_ref[3][14] = {
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{
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{ 0xe7b2, 0x50 },
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{ 0xe7b3, 0x00 },
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{ 0xe7b4, 0xcc },
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{ 0xe7b5, 0x44 },
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{ 0xe7b6, 0x81 },
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{ 0xe7b7, 0x30 },
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{ 0xe7b8, 0x07 },
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{ 0xe7b9, 0x10 },
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{ 0xe7ba, 0x01 },
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{ 0xe7bb, 0x00 },
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{ 0xe7bc, 0x00 },
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{ 0xe7bd, 0x00 },
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{ 0xe7be, 0x52 },
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{ 0xe7bf, 0x00 },
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}, {
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{ 0xe7b2, 0x50 },
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{ 0xe7b3, 0x00 },
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{ 0xe7b4, 0x00 },
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{ 0xe7b5, 0x40 },
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{ 0xe7b6, 0x6c },
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{ 0xe7b7, 0x20 },
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{ 0xe7b8, 0x07 },
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{ 0xe7b9, 0x00 },
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{ 0xe7ba, 0x01 },
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{ 0xe7bb, 0x00 },
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{ 0xe7bc, 0x00 },
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{ 0xe7bd, 0x00 },
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{ 0xe7be, 0x52 },
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{ 0xe7bf, 0x00 },
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}, {
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{ 0xe7b2, 0x30 },
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{ 0xe7b3, 0x00 },
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{ 0xe7b4, 0x00 },
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{ 0xe7b5, 0x40 },
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{ 0xe7b6, 0x6c },
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{ 0xe7b7, 0x20 },
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{ 0xe7b8, 0x14 },
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{ 0xe7b9, 0x00 },
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{ 0xe7ba, 0x2e },
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{ 0xe7bb, 0x00 },
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{ 0xe7bc, 0x00 },
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{ 0xe7bd, 0x01 },
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{ 0xe7be, 0x32 },
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{ 0xe7bf, 0x00 },
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}
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};
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static int max96772_aux_dpcd_read(struct serdes *serdes, unsigned int reg, unsigned int *value)
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{
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serdes_reg_write(serdes, 0xe778, reg & 0xff);
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serdes_reg_write(serdes, 0xe779, (reg >> 8) & 0xff);
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serdes_reg_write(serdes, 0xe77c, (reg >> 16) & 0xff);
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serdes_reg_write(serdes, 0xe776, 0x10);
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serdes_reg_write(serdes, 0xe777, 0x80);
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/* FIXME */
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msleep(50);
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serdes_reg_read(serdes, 0xe77a, value);
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return 0;
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}
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static int max96772_panel_init(struct serdes *serdes)
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{
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return 0;
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}
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static int max96772_panel_prepare(struct serdes *serdes)
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{
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const struct drm_display_mode *mode = &serdes->serdes_panel->mode;
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u32 hfp, hsa, hbp, hact;
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u32 vact, vsa, vfp, vbp;
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u64 hwords, mvid;
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bool hsync_pol, vsync_pol;
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serdes_reg_write(serdes, 0xe790, serdes->serdes_panel->link_rate);
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serdes_reg_write(serdes, 0xe792, serdes->serdes_panel->lane_count);
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if (serdes->serdes_panel->ssc) {
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serdes_reg_write(serdes, 0xe7b0, 0x01);
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serdes_reg_write(serdes, 0xe7b1, 0x10);
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} else {
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serdes_reg_write(serdes, 0xe7b1, 0x00);
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}
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switch (serdes->serdes_panel->link_rate) {
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case DP_LINK_BW_5_4:
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serdes_multi_reg_write(serdes, max96772_clk_ref[2],
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ARRAY_SIZE(max96772_clk_ref[2]));
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break;
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case DP_LINK_BW_2_7:
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serdes_multi_reg_write(serdes, max96772_clk_ref[1],
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ARRAY_SIZE(max96772_clk_ref[1]));
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break;
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case DP_LINK_BW_1_62:
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default:
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serdes_multi_reg_write(serdes, max96772_clk_ref[0],
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ARRAY_SIZE(max96772_clk_ref[0]));
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break;
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}
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vact = mode->vdisplay;
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vsa = mode->vsync_end - mode->vsync_start;
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vfp = mode->vsync_start - mode->vdisplay;
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vbp = mode->vtotal - mode->vsync_end;
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hact = mode->hdisplay;
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hsa = mode->hsync_end - mode->hsync_start;
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hfp = mode->hsync_start - mode->hdisplay;
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hbp = mode->htotal - mode->hsync_end;
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serdes_reg_write(serdes, 0xe794, hact & 0xff);
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serdes_reg_write(serdes, 0xe795, (hact >> 8) & 0xff);
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serdes_reg_write(serdes, 0xe796, hfp & 0xff);
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serdes_reg_write(serdes, 0xe797, (hfp >> 8) & 0xff);
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serdes_reg_write(serdes, 0xe798, hsa & 0xff);
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serdes_reg_write(serdes, 0xe799, (hsa >> 8) & 0xff);
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serdes_reg_write(serdes, 0xe79a, hbp & 0xff);
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serdes_reg_write(serdes, 0xe79b, (hbp >> 8) & 0xff);
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serdes_reg_write(serdes, 0xe79c, vact & 0xff);
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serdes_reg_write(serdes, 0xe79d, (vact >> 8) & 0xff);
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serdes_reg_write(serdes, 0xe79e, vfp & 0xff);
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serdes_reg_write(serdes, 0xe79f, (vfp >> 8) & 0xff);
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serdes_reg_write(serdes, 0xe7a0, vsa & 0xff);
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serdes_reg_write(serdes, 0xe7a1, (vsa >> 8) & 0xff);
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serdes_reg_write(serdes, 0xe7a2, vbp & 0xff);
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serdes_reg_write(serdes, 0xe7a3, (vbp >> 8) & 0xff);
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hsync_pol = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
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vsync_pol = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
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serdes_reg_write(serdes, 0xe7ac, hsync_pol | (vsync_pol << 1));
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/* NVID should always be set to 0x8000 */
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serdes_reg_write(serdes, 0xe7a8, 0);
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serdes_reg_write(serdes, 0xe7a9, 0x80);
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/* HWORDS = ((HRES x bits / pixel) / 16) - LANE_COUNT */
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hwords = DIV_ROUND_CLOSEST_ULL(hact * 24, 16) - serdes->serdes_panel->lane_count;
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serdes_reg_write(serdes, 0xe7a4, hwords);
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serdes_reg_write(serdes, 0xe7a5, hwords >> 8);
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/* MVID = (PCLK x NVID) x 10 / Link Rate */
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mvid = DIV_ROUND_CLOSEST_ULL((u64)mode->clock * 32768,
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drm_dp_bw_code_to_link_rate(serdes->serdes_panel->link_rate));
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serdes_reg_write(serdes, 0xe7a6, mvid & 0xff);
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serdes_reg_write(serdes, 0xe7a7, (mvid >> 8) & 0xff);
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serdes_reg_write(serdes, 0xe7aa, 0x40);
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serdes_reg_write(serdes, 0xe7ab, 0x00);
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return 0;
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}
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static int max96772_panel_unprepare(struct serdes *serdes)
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{
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return 0;
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}
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static int max96772_panel_enable(struct serdes *serdes)
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{
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u32 status[2];
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u32 val;
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int ret;
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/* Run link training */
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serdes_reg_write(serdes, 0xe776, 0x02);
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serdes_reg_write(serdes, 0xe777, 0x80);
|
|
ret = regmap_read_poll_timeout(serdes->regmap, 0x07f0, val,
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val & 0x01, MSEC_PER_SEC,
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500 * MSEC_PER_SEC);
|
if (!ret)
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return 0;
|
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ret = max96772_aux_dpcd_read(serdes, DP_LANE0_1_STATUS, &status[0]);
|
if (ret)
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return ret;
|
|
ret = max96772_aux_dpcd_read(serdes, DP_LANE2_3_STATUS, &status[1]);
|
if (ret)
|
return ret;
|
|
dev_err(serdes->dev, "Link Training failed: LANE0_1_STATUS=0x%02x, LANE2_3_STATUS=0x%02x\n",
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status[0], status[1]);
|
|
return 0;
|
}
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static int max96772_panel_disable(struct serdes *serdes)
|
{
|
return 0;
|
}
|
|
static struct serdes_chip_panel_ops max96772_panel_ops = {
|
.init = max96772_panel_init,
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.prepare = max96772_panel_prepare,
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.unprepare = max96772_panel_unprepare,
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.enable = max96772_panel_enable,
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.disable = max96772_panel_disable,
|
};
|
|
static int max96772_pinctrl_set_mux(struct serdes *serdes,
|
unsigned int function, unsigned int group)
|
{
|
struct serdes_pinctrl *pinctrl = serdes->pinctrl;
|
struct function_desc *func;
|
struct group_desc *grp;
|
int i;
|
u16 ms;
|
|
func = pinmux_generic_get_function(pinctrl->pctl, function);
|
if (!func)
|
return -EINVAL;
|
|
grp = pinctrl_generic_get_group(pinctrl->pctl, group);
|
if (!grp)
|
return -EINVAL;
|
|
SERDES_DBG_CHIP("%s: serdes chip %s func=%s data=%p group=%s data=%p, num_pin=%d\n",
|
__func__, serdes->chip_data->name, func->name,
|
func->data, grp->name, grp->data, grp->num_pins);
|
|
if (func->data) {
|
struct serdes_function_data *fdata = func->data;
|
|
ms = fdata->mdelay;
|
for (i = 0; i < grp->num_pins; i++) {
|
if (!ms) {
|
serdes_set_bits(serdes, GPIO_A_REG(grp->pins[i] - pinctrl->pin_base),
|
GPIO_OUT_DIS | GPIO_RX_EN | GPIO_TX_EN | GPIO_OUT,
|
FIELD_PREP(GPIO_OUT_DIS, fdata->gpio_out_dis) |
|
FIELD_PREP(GPIO_RX_EN, fdata->gpio_rx_en) |
|
FIELD_PREP(GPIO_TX_EN, fdata->gpio_tx_en) |
|
FIELD_PREP(GPIO_OUT, fdata->gpio_out_level));
|
if (fdata->gpio_tx_en)
|
serdes_set_bits(serdes,
|
GPIO_B_REG(grp->pins[i] - pinctrl->pin_base),
|
GPIO_TX_ID,
|
FIELD_PREP(GPIO_TX_ID, fdata->gpio_tx_id));
|
if (fdata->gpio_rx_en)
|
serdes_set_bits(serdes,
|
GPIO_C_REG(grp->pins[i] - pinctrl->pin_base),
|
GPIO_RX_ID,
|
FIELD_PREP(GPIO_RX_ID, fdata->gpio_rx_id));
|
} else {
|
mdelay(ms);
|
SERDES_DBG_CHIP("%s: delay %d ms\n",
|
__func__, ms);
|
}
|
}
|
}
|
|
if (grp->data) {
|
struct serdes_group_data *gdata = grp->data;
|
|
for (i = 0; i < gdata->num_configs; i++) {
|
const struct config_desc *config = &gdata->configs[i];
|
|
serdes_set_bits(serdes, config->reg,
|
config->mask, config->val);
|
}
|
}
|
|
return 0;
|
}
|
|
static int max96772_pinctrl_config_get(struct serdes *serdes,
|
unsigned int pin, unsigned long *config)
|
{
|
enum pin_config_param param = pinconf_to_config_param(*config);
|
unsigned int gpio_a_reg, gpio_b_reg;
|
u16 arg = 0;
|
|
serdes_reg_read(serdes, GPIO_A_REG(pin), &gpio_a_reg);
|
serdes_reg_read(serdes, GPIO_B_REG(pin), &gpio_b_reg);
|
|
SERDES_DBG_CHIP("%s: serdes chip %s pin=%d param=%d\n", __func__,
|
serdes->chip_data->name, pin, param);
|
|
switch (param) {
|
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
|
if (FIELD_GET(OUT_TYPE, gpio_b_reg))
|
return -EINVAL;
|
break;
|
case PIN_CONFIG_DRIVE_PUSH_PULL:
|
if (!FIELD_GET(OUT_TYPE, gpio_b_reg))
|
return -EINVAL;
|
break;
|
case PIN_CONFIG_BIAS_DISABLE:
|
if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 0)
|
return -EINVAL;
|
break;
|
case PIN_CONFIG_BIAS_PULL_UP:
|
if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 1)
|
return -EINVAL;
|
switch (FIELD_GET(RES_CFG, gpio_a_reg)) {
|
case 0:
|
arg = 40000;
|
break;
|
case 1:
|
arg = 10000;
|
break;
|
}
|
break;
|
case PIN_CONFIG_BIAS_PULL_DOWN:
|
if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 2)
|
return -EINVAL;
|
switch (FIELD_GET(RES_CFG, gpio_a_reg)) {
|
case 0:
|
arg = 40000;
|
break;
|
case 1:
|
arg = 10000;
|
break;
|
}
|
break;
|
case PIN_CONFIG_OUTPUT:
|
if (FIELD_GET(GPIO_OUT_DIS, gpio_a_reg))
|
return -EINVAL;
|
|
arg = FIELD_GET(GPIO_OUT, gpio_a_reg);
|
break;
|
default:
|
return -EOPNOTSUPP;
|
}
|
|
*config = pinconf_to_config_packed(param, arg);
|
|
return 0;
|
}
|
|
static int max96772_pinctrl_config_set(struct serdes *serdes,
|
unsigned int pin, unsigned long *configs,
|
unsigned int num_configs)
|
{
|
enum pin_config_param param;
|
u32 arg;
|
u8 res_cfg;
|
int i;
|
|
for (i = 0; i < num_configs; i++) {
|
param = pinconf_to_config_param(configs[i]);
|
arg = pinconf_to_config_argument(configs[i]);
|
|
SERDES_DBG_CHIP("%s: serdes chip %s pin=%d param=%d\n", __func__,
|
serdes->chip_data->name, pin, param);
|
|
switch (param) {
|
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
|
serdes_set_bits(serdes, GPIO_B_REG(pin),
|
OUT_TYPE, FIELD_PREP(OUT_TYPE, 0));
|
break;
|
case PIN_CONFIG_DRIVE_PUSH_PULL:
|
serdes_set_bits(serdes, GPIO_B_REG(pin),
|
OUT_TYPE, FIELD_PREP(OUT_TYPE, 1));
|
break;
|
case PIN_CONFIG_BIAS_DISABLE:
|
serdes_set_bits(serdes, GPIO_C_REG(pin),
|
PULL_UPDN_SEL,
|
FIELD_PREP(PULL_UPDN_SEL, 0));
|
break;
|
case PIN_CONFIG_BIAS_PULL_UP:
|
switch (arg) {
|
case 40000:
|
res_cfg = 0;
|
break;
|
case 1000000:
|
res_cfg = 1;
|
break;
|
default:
|
return -EINVAL;
|
}
|
|
serdes_set_bits(serdes, GPIO_A_REG(pin),
|
RES_CFG, FIELD_PREP(RES_CFG, res_cfg));
|
serdes_set_bits(serdes, GPIO_C_REG(pin),
|
PULL_UPDN_SEL,
|
FIELD_PREP(PULL_UPDN_SEL, 1));
|
break;
|
case PIN_CONFIG_BIAS_PULL_DOWN:
|
switch (arg) {
|
case 40000:
|
res_cfg = 0;
|
break;
|
case 1000000:
|
res_cfg = 1;
|
break;
|
default:
|
return -EINVAL;
|
}
|
|
serdes_set_bits(serdes, GPIO_A_REG(pin),
|
RES_CFG, FIELD_PREP(RES_CFG, res_cfg));
|
serdes_set_bits(serdes, GPIO_C_REG(pin),
|
PULL_UPDN_SEL,
|
FIELD_PREP(PULL_UPDN_SEL, 2));
|
break;
|
case PIN_CONFIG_OUTPUT:
|
serdes_set_bits(serdes, GPIO_A_REG(pin),
|
GPIO_OUT_DIS | GPIO_OUT,
|
FIELD_PREP(GPIO_OUT_DIS, 0) |
|
FIELD_PREP(GPIO_OUT, arg));
|
break;
|
default:
|
return -EOPNOTSUPP;
|
}
|
}
|
|
return 0;
|
}
|
|
static struct serdes_chip_pinctrl_ops max96772_pinctrl_ops = {
|
.pin_config_get = max96772_pinctrl_config_get,
|
.pin_config_set = max96772_pinctrl_config_set,
|
.set_mux = max96772_pinctrl_set_mux,
|
};
|
|
static int max96772_gpio_direction_input(struct serdes *serdes, int gpio)
|
{
|
return 0;
|
}
|
|
static int max96772_gpio_direction_output(struct serdes *serdes, int gpio, int value)
|
{
|
return 0;
|
}
|
|
static int max96772_gpio_get_level(struct serdes *serdes, int gpio)
|
{
|
return 0;
|
}
|
|
static int max96772_gpio_set_level(struct serdes *serdes, int gpio, int value)
|
{
|
return 0;
|
}
|
|
static int max96772_gpio_set_config(struct serdes *serdes, int gpio, unsigned long config)
|
{
|
return 0;
|
}
|
|
static int max96772_gpio_to_irq(struct serdes *serdes, int gpio)
|
{
|
return 0;
|
}
|
|
static struct serdes_chip_gpio_ops max96772_gpio_ops = {
|
.direction_input = max96772_gpio_direction_input,
|
.direction_output = max96772_gpio_direction_output,
|
.get_level = max96772_gpio_get_level,
|
.set_level = max96772_gpio_set_level,
|
.set_config = max96772_gpio_set_config,
|
.to_irq = max96772_gpio_to_irq,
|
};
|
|
static int max96772_pm_suspend(struct serdes *serdes)
|
{
|
return 0;
|
}
|
|
static int max96772_pm_resume(struct serdes *serdes)
|
{
|
return 0;
|
}
|
|
static struct serdes_chip_pm_ops max96772_pm_ops = {
|
.suspend = max96772_pm_suspend,
|
.resume = max96772_pm_resume,
|
};
|
|
static int max96772_irq_lock_handle(struct serdes *serdes)
|
{
|
return IRQ_HANDLED;
|
}
|
|
static int max96772_irq_err_handle(struct serdes *serdes)
|
{
|
return IRQ_HANDLED;
|
}
|
|
static struct serdes_chip_irq_ops max96772_irq_ops = {
|
.lock_handle = max96772_irq_lock_handle,
|
.err_handle = max96772_irq_err_handle,
|
};
|
|
struct serdes_chip_data serdes_max96772_data = {
|
.name = "max96772",
|
.serdes_type = TYPE_DES,
|
.serdes_id = MAXIM_ID_MAX96772,
|
.connector_type = DRM_MODE_CONNECTOR_eDP,
|
.regmap_config = &max96772_regmap_config,
|
.pinctrl_info = &max96772_pinctrl_info,
|
.panel_ops = &max96772_panel_ops,
|
.pinctrl_ops = &max96772_pinctrl_ops,
|
.gpio_ops = &max96772_gpio_ops,
|
.pm_ops = &max96772_pm_ops,
|
.irq_ops = &max96772_irq_ops,
|
};
|
EXPORT_SYMBOL_GPL(serdes_max96772_data);
|
|
MODULE_LICENSE("GPL");
|
