/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* maxim-max96752.h -- register define for max96752 chip
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*
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* Copyright (c) 2023-2028 Rockchip Electronics Co. Ltd.
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*
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* Author:
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*
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*/
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#ifndef __MFD_SERDES_MAXIM_MAX96752_H__
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#define __MFD_SERDES_MAXIM_MAX96752_H__
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#define GPIO_A_REG(gpio) (0x0200 + ((gpio) * 3))
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#define GPIO_B_REG(gpio) (0x0201 + ((gpio) * 3))
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#define GPIO_C_REG(gpio) (0x0202 + ((gpio) * 3))
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/* 0200h */
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#define RES_CFG BIT(7)
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#define RSVD BIT(6)
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#define TX_COMP_EN BIT(5)
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#define GPIO_OUT BIT(4)
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#define GPIO_IN BIT(3)
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#define GPIO_RX_EN BIT(2)
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#define GPIO_TX_EN BIT(1)
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#define GPIO_OUT_DIS BIT(0)
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/* 0201h */
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#define PULL_UPDN_SEL GENMASK(7, 6)
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#define OUT_TYPE BIT(5)
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#define GPIO_TX_ID GENMASK(4, 0)
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/* 0202h */
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#define OVR_RES_CFG BIT(7)
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#define GPIO_RX_ID GENMASK(4, 0)
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enum link_mode {
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DUAL_LINK,
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LINKA,
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LINKB,
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SPLITTER_MODE,
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};
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#endif
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