/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* AFE440X Heart Rate Monitors and Low-Cost Pulse Oximeters
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*
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* Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com/
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* Andrew F. Davis <afd@ti.com>
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*/
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#ifndef _AFE440X_H
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#define _AFE440X_H
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/* AFE440X registers */
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#define AFE440X_CONTROL0 0x00
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#define AFE440X_LED2STC 0x01
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#define AFE440X_LED2ENDC 0x02
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#define AFE440X_LED1LEDSTC 0x03
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#define AFE440X_LED1LEDENDC 0x04
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#define AFE440X_ALED2STC 0x05
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#define AFE440X_ALED2ENDC 0x06
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#define AFE440X_LED1STC 0x07
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#define AFE440X_LED1ENDC 0x08
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#define AFE440X_LED2LEDSTC 0x09
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#define AFE440X_LED2LEDENDC 0x0a
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#define AFE440X_ALED1STC 0x0b
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#define AFE440X_ALED1ENDC 0x0c
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#define AFE440X_LED2CONVST 0x0d
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#define AFE440X_LED2CONVEND 0x0e
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#define AFE440X_ALED2CONVST 0x0f
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#define AFE440X_ALED2CONVEND 0x10
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#define AFE440X_LED1CONVST 0x11
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#define AFE440X_LED1CONVEND 0x12
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#define AFE440X_ALED1CONVST 0x13
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#define AFE440X_ALED1CONVEND 0x14
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#define AFE440X_ADCRSTSTCT0 0x15
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#define AFE440X_ADCRSTENDCT0 0x16
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#define AFE440X_ADCRSTSTCT1 0x17
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#define AFE440X_ADCRSTENDCT1 0x18
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#define AFE440X_ADCRSTSTCT2 0x19
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#define AFE440X_ADCRSTENDCT2 0x1a
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#define AFE440X_ADCRSTSTCT3 0x1b
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#define AFE440X_ADCRSTENDCT3 0x1c
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#define AFE440X_PRPCOUNT 0x1d
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#define AFE440X_CONTROL1 0x1e
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#define AFE440X_LEDCNTRL 0x22
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#define AFE440X_CONTROL2 0x23
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#define AFE440X_ALARM 0x29
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#define AFE440X_LED2VAL 0x2a
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#define AFE440X_ALED2VAL 0x2b
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#define AFE440X_LED1VAL 0x2c
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#define AFE440X_ALED1VAL 0x2d
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#define AFE440X_LED2_ALED2VAL 0x2e
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#define AFE440X_LED1_ALED1VAL 0x2f
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#define AFE440X_CONTROL3 0x31
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#define AFE440X_PDNCYCLESTC 0x32
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#define AFE440X_PDNCYCLEENDC 0x33
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/* CONTROL0 register fields */
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#define AFE440X_CONTROL0_REG_READ BIT(0)
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#define AFE440X_CONTROL0_TM_COUNT_RST BIT(1)
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#define AFE440X_CONTROL0_SW_RESET BIT(3)
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/* CONTROL1 register fields */
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#define AFE440X_CONTROL1_TIMEREN BIT(8)
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/* TIAGAIN register fields */
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#define AFE440X_TIAGAIN_ENSEPGAIN BIT(15)
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/* CONTROL2 register fields */
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#define AFE440X_CONTROL2_PDN_AFE BIT(0)
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#define AFE440X_CONTROL2_PDN_RX BIT(1)
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#define AFE440X_CONTROL2_DYNAMIC4 BIT(3)
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#define AFE440X_CONTROL2_DYNAMIC3 BIT(4)
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#define AFE440X_CONTROL2_DYNAMIC2 BIT(14)
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#define AFE440X_CONTROL2_DYNAMIC1 BIT(20)
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/* CONTROL3 register fields */
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#define AFE440X_CONTROL3_CLKDIV GENMASK(2, 0)
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/* CONTROL0 values */
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#define AFE440X_CONTROL0_WRITE 0x0
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#define AFE440X_CONTROL0_READ 0x1
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#define AFE440X_INTENSITY_CHAN(_index, _mask) \
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{ \
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.type = IIO_INTENSITY, \
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.channel = _index, \
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.address = _index, \
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.scan_index = _index, \
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.scan_type = { \
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.sign = 's', \
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.realbits = 24, \
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.storagebits = 32, \
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.endianness = IIO_CPU, \
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}, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
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_mask, \
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.indexed = true, \
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}
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#define AFE440X_CURRENT_CHAN(_index) \
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{ \
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.type = IIO_CURRENT, \
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.channel = _index, \
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.address = _index, \
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.scan_index = -1, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
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BIT(IIO_CHAN_INFO_SCALE), \
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.indexed = true, \
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.output = true, \
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}
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struct afe440x_val_table {
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int integer;
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int fract;
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};
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#define AFE440X_TABLE_ATTR(_name, _table) \
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static ssize_t _name ## _show(struct device *dev, \
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struct device_attribute *attr, char *buf) \
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{ \
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ssize_t len = 0; \
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int i; \
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\
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for (i = 0; i < ARRAY_SIZE(_table); i++) \
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len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06u ", \
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_table[i].integer, \
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_table[i].fract); \
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\
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buf[len - 1] = '\n'; \
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\
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return len; \
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} \
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static DEVICE_ATTR_RO(_name)
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struct afe440x_attr {
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struct device_attribute dev_attr;
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unsigned int field;
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const struct afe440x_val_table *val_table;
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unsigned int table_size;
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};
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#define to_afe440x_attr(_dev_attr) \
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container_of(_dev_attr, struct afe440x_attr, dev_attr)
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#define AFE440X_ATTR(_name, _field, _table) \
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struct afe440x_attr afe440x_attr_##_name = { \
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.dev_attr = __ATTR(_name, (S_IRUGO | S_IWUSR), \
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afe440x_show_register, \
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afe440x_store_register), \
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.field = _field, \
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.val_table = _table, \
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.table_size = ARRAY_SIZE(_table), \
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}
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#endif /* _AFE440X_H */
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