/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* drivers/i2c/busses/i2c-ibm_iic.h
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*
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* Support for the IIC peripheral on IBM PPC 4xx
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*
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* Copyright (c) 2003 Zultys Technologies.
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* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
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*
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* Based on original work by
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* Ian DaSilva <idasilva@mvista.com>
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* Armin Kuster <akuster@mvista.com>
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* Matt Porter <mporter@mvista.com>
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*
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* Copyright 2000-2003 MontaVista Software Inc.
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*/
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#ifndef __I2C_IBM_IIC_H_
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#define __I2C_IBM_IIC_H_
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#include <linux/i2c.h>
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struct iic_regs {
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u16 mdbuf;
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u16 sbbuf;
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u8 lmadr;
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u8 hmadr;
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u8 cntl;
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u8 mdcntl;
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u8 sts;
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u8 extsts;
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u8 lsadr;
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u8 hsadr;
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u8 clkdiv;
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u8 intmsk;
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u8 xfrcnt;
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u8 xtcntlss;
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u8 directcntl;
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};
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struct ibm_iic_private {
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struct i2c_adapter adap;
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volatile struct iic_regs __iomem *vaddr;
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wait_queue_head_t wq;
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int idx;
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int irq;
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int fast_mode;
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u8 clckdiv;
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};
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/* IICx_CNTL register */
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#define CNTL_HMT 0x80
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#define CNTL_AMD 0x40
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#define CNTL_TCT_MASK 0x30
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#define CNTL_TCT_SHIFT 4
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#define CNTL_RPST 0x08
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#define CNTL_CHT 0x04
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#define CNTL_RW 0x02
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#define CNTL_PT 0x01
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/* IICx_MDCNTL register */
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#define MDCNTL_FSDB 0x80
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#define MDCNTL_FMDB 0x40
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#define MDCNTL_EGC 0x20
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#define MDCNTL_FSM 0x10
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#define MDCNTL_ESM 0x08
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#define MDCNTL_EINT 0x04
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#define MDCNTL_EUBS 0x02
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#define MDCNTL_HSCL 0x01
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/* IICx_STS register */
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#define STS_SSS 0x80
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#define STS_SLPR 0x40
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#define STS_MDBS 0x20
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#define STS_MDBF 0x10
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#define STS_SCMP 0x08
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#define STS_ERR 0x04
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#define STS_IRQA 0x02
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#define STS_PT 0x01
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/* IICx_EXTSTS register */
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#define EXTSTS_IRQP 0x80
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#define EXTSTS_BCS_MASK 0x70
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#define EXTSTS_BCS_FREE 0x40
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#define EXTSTS_IRQD 0x08
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#define EXTSTS_LA 0x04
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#define EXTSTS_ICT 0x02
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#define EXTSTS_XFRA 0x01
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/* IICx_INTRMSK register */
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#define INTRMSK_EIRC 0x80
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#define INTRMSK_EIRS 0x40
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#define INTRMSK_EIWC 0x20
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#define INTRMSK_EIWS 0x10
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#define INTRMSK_EIHE 0x08
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#define INTRMSK_EIIC 0x04
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#define INTRMSK_EITA 0x02
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#define INTRMSK_EIMTC 0x01
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/* IICx_XFRCNT register */
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#define XFRCNT_MTC_MASK 0x07
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/* IICx_XTCNTLSS register */
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#define XTCNTLSS_SRC 0x80
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#define XTCNTLSS_SRS 0x40
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#define XTCNTLSS_SWC 0x20
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#define XTCNTLSS_SWS 0x10
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#define XTCNTLSS_SRST 0x01
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/* IICx_DIRECTCNTL register */
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#define DIRCNTL_SDAC 0x08
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#define DIRCNTL_SCC 0x04
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#define DIRCNTL_MSDA 0x02
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#define DIRCNTL_MSC 0x01
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/* Check if we really control the I2C bus and bus is free */
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#define DIRCTNL_FREE(v) (((v) & 0x0f) == 0x0f)
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#endif /* __I2C_IBM_IIC_H_ */
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