/* SPDX-License-Identifier: MIT */
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#ifndef __NVKM_DEVICE_TEGRA_H__
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#define __NVKM_DEVICE_TEGRA_H__
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#include <core/device.h>
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#include <core/mm.h>
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struct nvkm_device_tegra {
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const struct nvkm_device_tegra_func *func;
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struct nvkm_device device;
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struct platform_device *pdev;
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int irq;
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struct reset_control *rst;
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struct clk *clk;
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struct clk *clk_ref;
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struct clk *clk_pwr;
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struct regulator *vdd;
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struct {
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/*
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* Protects accesses to mm from subsystems
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*/
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struct mutex mutex;
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struct nvkm_mm mm;
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struct iommu_domain *domain;
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unsigned long pgshift;
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} iommu;
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int gpu_speedo;
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int gpu_speedo_id;
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};
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struct nvkm_device_tegra_func {
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/*
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* If an IOMMU is used, indicates which address bit will trigger a
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* IOMMU translation when set (when this bit is not set, IOMMU is
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* bypassed). A value of 0 means an IOMMU is never used.
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*/
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u8 iommu_bit;
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/*
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* Whether the chip requires a reference clock
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*/
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bool require_ref_clk;
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/*
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* Whether the chip requires the VDD regulator
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*/
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bool require_vdd;
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};
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int nvkm_device_tegra_new(const struct nvkm_device_tegra_func *,
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struct platform_device *,
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const char *cfg, const char *dbg,
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bool detect, bool mmio, u64 subdev_mask,
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struct nvkm_device **);
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#endif
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