// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: jitao.shi <jitao.shi@mediatek.com>
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*/
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#include "mtk_mipi_tx.h"
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#define MIPITX_LANE_CON 0x000c
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#define RG_DSI_CPHY_T1DRV_EN BIT(0)
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#define RG_DSI_ANA_CK_SEL BIT(1)
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#define RG_DSI_PHY_CK_SEL BIT(2)
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#define RG_DSI_CPHY_EN BIT(3)
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#define RG_DSI_PHYCK_INV_EN BIT(4)
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#define RG_DSI_PWR04_EN BIT(5)
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#define RG_DSI_BG_LPF_EN BIT(6)
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#define RG_DSI_BG_CORE_EN BIT(7)
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#define RG_DSI_PAD_TIEL_SEL BIT(8)
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#define MIPITX_VOLTAGE_SEL 0x0010
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#define RG_DSI_HSTX_LDO_REF_SEL (0xf << 6)
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#define MIPITX_PLL_PWR 0x0028
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#define MIPITX_PLL_CON0 0x002c
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#define MIPITX_PLL_CON1 0x0030
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#define MIPITX_PLL_CON2 0x0034
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#define MIPITX_PLL_CON3 0x0038
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#define MIPITX_PLL_CON4 0x003c
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#define RG_DSI_PLL_IBIAS (3 << 10)
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#define MIPITX_D2P_RTCODE 0x0100
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#define MIPITX_D2_SW_CTL_EN 0x0144
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#define MIPITX_D0_SW_CTL_EN 0x0244
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#define MIPITX_CK_CKMODE_EN 0x0328
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#define DSI_CK_CKMODE_EN BIT(0)
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#define MIPITX_CK_SW_CTL_EN 0x0344
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#define MIPITX_D1_SW_CTL_EN 0x0444
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#define MIPITX_D3_SW_CTL_EN 0x0544
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#define DSI_SW_CTL_EN BIT(0)
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#define AD_DSI_PLL_SDM_PWR_ON BIT(0)
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#define AD_DSI_PLL_SDM_ISO_EN BIT(1)
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#define RG_DSI_PLL_EN BIT(4)
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#define RG_DSI_PLL_POSDIV (0x7 << 8)
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static int mtk_mipi_tx_pll_enable(struct clk_hw *hw)
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{
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struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
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unsigned int txdiv, txdiv0;
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u64 pcw;
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dev_dbg(mipi_tx->dev, "enable: %u bps\n", mipi_tx->data_rate);
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if (mipi_tx->data_rate >= 2000000000) {
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txdiv = 1;
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txdiv0 = 0;
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} else if (mipi_tx->data_rate >= 1000000000) {
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txdiv = 2;
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txdiv0 = 1;
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} else if (mipi_tx->data_rate >= 500000000) {
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txdiv = 4;
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txdiv0 = 2;
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} else if (mipi_tx->data_rate > 250000000) {
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txdiv = 8;
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txdiv0 = 3;
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} else if (mipi_tx->data_rate >= 125000000) {
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txdiv = 16;
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txdiv0 = 4;
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} else {
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return -EINVAL;
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}
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS);
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mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN);
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udelay(1);
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
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pcw = div_u64(((u64)mipi_tx->data_rate * txdiv) << 24, 26000000);
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writel(pcw, mipi_tx->regs + MIPITX_PLL_CON0);
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mtk_mipi_tx_update_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV,
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txdiv0 << 8);
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mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN);
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return 0;
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}
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static void mtk_mipi_tx_pll_disable(struct clk_hw *hw)
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{
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struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN);
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mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
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}
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static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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return clamp_val(rate, 50000000, 1600000000);
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}
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static const struct clk_ops mtk_mipi_tx_pll_ops = {
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.enable = mtk_mipi_tx_pll_enable,
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.disable = mtk_mipi_tx_pll_disable,
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.round_rate = mtk_mipi_tx_pll_round_rate,
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.set_rate = mtk_mipi_tx_pll_set_rate,
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.recalc_rate = mtk_mipi_tx_pll_recalc_rate,
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};
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static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx)
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{
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int i, j;
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for (i = 0; i < 5; i++) {
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if ((mipi_tx->rt_code[i] & 0x1f) == 0)
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mipi_tx->rt_code[i] |= 0x10;
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if ((mipi_tx->rt_code[i] >> 5 & 0x1f) == 0)
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mipi_tx->rt_code[i] |= 0x10 << 5;
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for (j = 0; j < 10; j++)
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mtk_mipi_tx_update_bits(mipi_tx,
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MIPITX_D2P_RTCODE * (i + 1) + j * 4,
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1, mipi_tx->rt_code[i] >> j & 1);
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}
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}
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static void mtk_mipi_tx_power_on_signal(struct phy *phy)
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{
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struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
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/* BG_LPF_EN / BG_CORE_EN */
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writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN,
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mipi_tx->regs + MIPITX_LANE_CON);
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usleep_range(30, 100);
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writel(RG_DSI_BG_CORE_EN | RG_DSI_BG_LPF_EN,
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mipi_tx->regs + MIPITX_LANE_CON);
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/* Switch OFF each Lane */
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
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mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
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mtk_mipi_tx_update_bits(mipi_tx, MIPITX_VOLTAGE_SEL,
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RG_DSI_HSTX_LDO_REF_SEL,
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(mipi_tx->mipitx_drive - 3000) / 200 << 6);
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mtk_mipi_tx_config_calibration_data(mipi_tx);
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mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
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}
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static void mtk_mipi_tx_power_off_signal(struct phy *phy)
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{
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struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
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/* Switch ON each Lane */
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mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
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mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
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mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
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mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
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mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
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writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN,
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mipi_tx->regs + MIPITX_LANE_CON);
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writel(RG_DSI_PAD_TIEL_SEL, mipi_tx->regs + MIPITX_LANE_CON);
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}
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const struct mtk_mipitx_data mt8183_mipitx_data = {
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.mipi_tx_clk_ops = &mtk_mipi_tx_pll_ops,
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.mipi_tx_enable_signal = mtk_mipi_tx_power_on_signal,
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.mipi_tx_disable_signal = mtk_mipi_tx_power_off_signal,
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};
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