/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#define SWSMU_CODE_LAYER_L3
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#include <linux/firmware.h>
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#include "amdgpu.h"
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#include "amdgpu_smu.h"
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#include "atomfirmware.h"
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#include "amdgpu_atomfirmware.h"
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#include "smu_v12_0.h"
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#include "soc15_common.h"
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#include "atom.h"
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#include "smu_cmn.h"
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#include "asic_reg/mp/mp_12_0_0_offset.h"
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#include "asic_reg/mp/mp_12_0_0_sh_mask.h"
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#include "asic_reg/smuio/smuio_12_0_0_offset.h"
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#include "asic_reg/smuio/smuio_12_0_0_sh_mask.h"
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/*
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* DO NOT use these for err/warn/info/debug messages.
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* Use dev_err, dev_warn, dev_info and dev_dbg instead.
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* They are more MGPU friendly.
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*/
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#undef pr_err
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#undef pr_warn
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#undef pr_info
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#undef pr_debug
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// because some SMU12 based ASICs use older ip offset tables
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// we should undefine this register from the smuio12 header
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// to prevent confusion down the road
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#undef mmPWR_MISC_CNTL_STATUS
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#define smnMP1_FIRMWARE_FLAGS 0x3010024
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int smu_v12_0_check_fw_status(struct smu_context *smu)
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{
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struct amdgpu_device *adev = smu->adev;
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uint32_t mp1_fw_flags;
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mp1_fw_flags = RREG32_PCIE(MP1_Public |
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(smnMP1_FIRMWARE_FLAGS & 0xffffffff));
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if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
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MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
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return 0;
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return -EIO;
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}
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int smu_v12_0_check_fw_version(struct smu_context *smu)
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{
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uint32_t if_version = 0xff, smu_version = 0xff;
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uint16_t smu_major;
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uint8_t smu_minor, smu_debug;
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int ret = 0;
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ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
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if (ret)
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return ret;
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smu_major = (smu_version >> 16) & 0xffff;
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smu_minor = (smu_version >> 8) & 0xff;
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smu_debug = (smu_version >> 0) & 0xff;
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/*
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* 1. if_version mismatch is not critical as our fw is designed
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* to be backward compatible.
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* 2. New fw usually brings some optimizations. But that's visible
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* only on the paired driver.
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* Considering above, we just leave user a warning message instead
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* of halt driver loading.
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*/
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if (if_version != smu->smc_driver_if_version) {
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dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
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"smu fw version = 0x%08x (%d.%d.%d)\n",
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smu->smc_driver_if_version, if_version,
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smu_version, smu_major, smu_minor, smu_debug);
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dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
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}
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return ret;
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}
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int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate)
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{
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if (!smu->is_apu)
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return 0;
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if (gate)
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return smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownSdma, NULL);
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else
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return smu_cmn_send_smc_msg(smu, SMU_MSG_PowerUpSdma, NULL);
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}
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int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
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{
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if (!(smu->adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
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return 0;
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return smu_cmn_send_smc_msg_with_param(smu,
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SMU_MSG_SetGfxCGPG,
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enable ? 1 : 0,
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NULL);
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}
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/**
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* smu_v12_0_get_gfxoff_status - get gfxoff status
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*
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* @smu: amdgpu_device pointer
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*
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* This function will be used to get gfxoff status
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*
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* Returns 0=GFXOFF(default).
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* Returns 1=Transition out of GFX State.
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* Returns 2=Not in GFXOFF.
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* Returns 3=Transition into GFXOFF.
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*/
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uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu)
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{
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uint32_t reg;
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uint32_t gfxOff_Status = 0;
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struct amdgpu_device *adev = smu->adev;
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reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL);
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gfxOff_Status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
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>> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
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return gfxOff_Status;
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}
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int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
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{
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int ret = 0, timeout = 500;
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if (enable) {
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ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
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} else {
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ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
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/* confirm gfx is back to "on" state, timeout is 0.5 second */
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while (!(smu_v12_0_get_gfxoff_status(smu) == 2)) {
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msleep(1);
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timeout--;
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if (timeout == 0) {
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DRM_ERROR("disable gfxoff timeout and failed!\n");
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break;
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}
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}
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}
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return ret;
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}
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int smu_v12_0_fini_smc_tables(struct smu_context *smu)
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{
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struct smu_table_context *smu_table = &smu->smu_table;
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kfree(smu_table->clocks_table);
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smu_table->clocks_table = NULL;
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kfree(smu_table->metrics_table);
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smu_table->metrics_table = NULL;
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kfree(smu_table->watermarks_table);
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smu_table->watermarks_table = NULL;
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kfree(smu_table->gpu_metrics_table);
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smu_table->gpu_metrics_table = NULL;
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return 0;
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}
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int smu_v12_0_set_default_dpm_tables(struct smu_context *smu)
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{
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struct smu_table_context *smu_table = &smu->smu_table;
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return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
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}
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int smu_v12_0_mode2_reset(struct smu_context *smu){
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return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2, NULL);
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}
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int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
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uint32_t min, uint32_t max)
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{
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int ret = 0;
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if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
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return 0;
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switch (clk_type) {
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case SMU_GFXCLK:
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case SMU_SCLK:
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ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, min, NULL);
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if (ret)
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return ret;
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ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, max, NULL);
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if (ret)
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return ret;
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break;
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case SMU_FCLK:
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case SMU_MCLK:
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case SMU_UCLK:
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ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min, NULL);
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if (ret)
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return ret;
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ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max, NULL);
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if (ret)
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return ret;
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break;
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case SMU_SOCCLK:
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ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min, NULL);
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if (ret)
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return ret;
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ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max, NULL);
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if (ret)
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return ret;
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break;
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case SMU_VCLK:
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ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinVcn, min, NULL);
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if (ret)
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return ret;
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ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxVcn, max, NULL);
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if (ret)
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return ret;
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break;
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default:
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return -EINVAL;
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}
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return ret;
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}
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int smu_v12_0_set_driver_table_location(struct smu_context *smu)
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{
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struct smu_table *driver_table = &smu->smu_table.driver_table;
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int ret = 0;
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if (driver_table->mc_address) {
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ret = smu_cmn_send_smc_msg_with_param(smu,
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SMU_MSG_SetDriverDramAddrHigh,
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upper_32_bits(driver_table->mc_address),
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NULL);
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if (!ret)
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ret = smu_cmn_send_smc_msg_with_param(smu,
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SMU_MSG_SetDriverDramAddrLow,
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lower_32_bits(driver_table->mc_address),
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NULL);
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}
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return ret;
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}
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void smu_v12_0_init_gpu_metrics_v2_0(struct gpu_metrics_v2_0 *gpu_metrics)
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{
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memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v2_0));
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gpu_metrics->common_header.structure_size =
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sizeof(struct gpu_metrics_v2_0);
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gpu_metrics->common_header.format_revision = 2;
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gpu_metrics->common_header.content_revision = 0;
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gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
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}
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