/*
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* VCE_3_0 Register documentation
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*
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* Copyright (C) 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef VCE_3_0_D_H
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#define VCE_3_0_D_H
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#define mmVCE_STATUS 0x8001
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#define mmVCE_VCPU_CNTL 0x8005
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#define mmVCE_VCPU_CACHE_OFFSET0 0x8009
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#define mmVCE_VCPU_CACHE_SIZE0 0x800a
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#define mmVCE_VCPU_CACHE_OFFSET1 0x800b
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#define mmVCE_VCPU_CACHE_SIZE1 0x800c
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#define mmVCE_VCPU_CACHE_OFFSET2 0x800d
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#define mmVCE_VCPU_CACHE_SIZE2 0x800e
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#define mmVCE_SOFT_RESET 0x8048
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#define mmVCE_RB_BASE_LO2 0x805b
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#define mmVCE_RB_BASE_HI2 0x805c
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#define mmVCE_RB_SIZE2 0x805d
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#define mmVCE_RB_RPTR2 0x805e
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#define mmVCE_RB_WPTR2 0x805f
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#define mmVCE_RB_BASE_LO 0x8060
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#define mmVCE_RB_BASE_HI 0x8061
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#define mmVCE_RB_SIZE 0x8062
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#define mmVCE_RB_RPTR 0x8063
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#define mmVCE_RB_WPTR 0x8064
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#define mmVCE_RB_ARB_CTRL 0x809f
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#define mmVCE_CLOCK_GATING_A 0x80be
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#define mmVCE_CLOCK_GATING_B 0x80bf
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#define mmVCE_RB_BASE_LO3 0x80d4
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#define mmVCE_RB_BASE_HI3 0x80d5
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#define mmVCE_RB_SIZE3 0x80d6
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#define mmVCE_RB_RPTR3 0x80d7
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#define mmVCE_RB_WPTR3 0x80d8
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#define mmVCE_UENC_DMA_DCLK_CTRL 0x8390
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#define mmVCE_UENC_CLOCK_GATING 0x81ef
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#define mmVCE_UENC_REG_CLOCK_GATING 0x81f0
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#define mmVCE_UENC_CLOCK_GATING_2 0x8210
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#define mmVCE_SYS_INT_EN 0x8540
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#define mmVCE_SYS_INT_STATUS 0x8541
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#define mmVCE_SYS_INT_ACK 0x8541
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#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR 0x8597
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#define mmVCE_LMI_CTRL2 0x859d
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#define mmVCE_LMI_SWAP_CNTL3 0x859e
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#define mmVCE_LMI_CTRL 0x85a6
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#define mmVCE_LMI_STATUS 0x85a7
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#define mmVCE_LMI_VM_CTRL 0x85a8
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#define mmVCE_LMI_SWAP_CNTL 0x85ad
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#define mmVCE_LMI_SWAP_CNTL1 0x85ae
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#define mmVCE_LMI_SWAP_CNTL2 0x85b3
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#define mmVCE_LMI_MISC_CTRL 0x85b5
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#define mmVCE_LMI_CACHE_CTRL 0x85bd
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#endif /* VCE_3_0_D_H */
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