/*
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* Copyright (C) 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _nbio_6_1_SMN_HEADER
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#define _nbio_6_1_SMN_HEADER
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#define smnCPM_CONTROL 0x11180460
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#define smnPCIE_CNTL2 0x11180070
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#define smnPCIE_CONFIG_CNTL 0x11180044
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#define smnPCIE_CI_CNTL 0x11180080
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#define smnPCIE_PERF_COUNT_CNTL 0x11180200
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#define smnPCIE_PERF_CNTL_TXCLK 0x11180204
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#define smnPCIE_PERF_COUNT0_TXCLK 0x11180208
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#define smnPCIE_PERF_COUNT1_TXCLK 0x1118020c
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#define smnPCIE_PERF_CNTL_MST_R_CLK 0x11180210
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#define smnPCIE_PERF_COUNT0_MST_R_CLK 0x11180214
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#define smnPCIE_PERF_COUNT1_MST_R_CLK 0x11180218
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#define smnPCIE_PERF_CNTL_MST_C_CLK 0x1118021c
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#define smnPCIE_PERF_COUNT0_MST_C_CLK 0x11180220
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#define smnPCIE_PERF_COUNT1_MST_C_CLK 0x11180224
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#define smnPCIE_PERF_CNTL_SLV_R_CLK 0x11180228
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#define smnPCIE_PERF_COUNT0_SLV_R_CLK 0x1118022c
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#define smnPCIE_PERF_COUNT1_SLV_R_CLK 0x11180230
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#define smnPCIE_PERF_CNTL_SLV_S_C_CLK 0x11180234
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#define smnPCIE_PERF_COUNT0_SLV_S_C_CLK 0x11180238
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#define smnPCIE_PERF_COUNT1_SLV_S_C_CLK 0x1118023c
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#define smnPCIE_PERF_CNTL_SLV_NS_C_CLK 0x11180240
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#define smnPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x11180244
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#define smnPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x11180248
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#define smnPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1118024c
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#define smnPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x11180250
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#define smnPCIE_PERF_CNTL_TXCLK2 0x11180254
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#define smnPCIE_PERF_COUNT0_TXCLK2 0x11180258
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#define smnPCIE_PERF_COUNT1_TXCLK2 0x1118025c
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#define smnPCIE_RX_NUM_NAK 0x11180038
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#define smnPCIE_RX_NUM_NAK_GENERATED 0x1118003c
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#endif // _nbio_6_1_SMN_HEADER
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