/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DAL_CLK_MGR_INTERNAL_H__
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#define __DAL_CLK_MGR_INTERNAL_H__
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#include "clk_mgr.h"
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#include "dc.h"
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/*
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* only thing needed from here is MEMORY_TYPE_MULTIPLIER_CZ, which is also
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* used in resource, perhaps this should be defined somewhere more common.
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*/
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#include "resource.h"
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/* Starting DID for each range */
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enum dentist_base_divider_id {
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DENTIST_BASE_DID_1 = 0x08,
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DENTIST_BASE_DID_2 = 0x40,
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DENTIST_BASE_DID_3 = 0x60,
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DENTIST_BASE_DID_4 = 0x7e,
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DENTIST_MAX_DID = 0x7f
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};
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/* Starting point and step size for each divider range.*/
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enum dentist_divider_range {
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DENTIST_DIVIDER_RANGE_1_START = 8, /* 2.00 */
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DENTIST_DIVIDER_RANGE_1_STEP = 1, /* 0.25 */
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DENTIST_DIVIDER_RANGE_2_START = 64, /* 16.00 */
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DENTIST_DIVIDER_RANGE_2_STEP = 2, /* 0.50 */
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DENTIST_DIVIDER_RANGE_3_START = 128, /* 32.00 */
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DENTIST_DIVIDER_RANGE_3_STEP = 4, /* 1.00 */
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DENTIST_DIVIDER_RANGE_4_START = 248, /* 62.00 */
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DENTIST_DIVIDER_RANGE_4_STEP = 264, /* 66.00 */
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DENTIST_DIVIDER_RANGE_SCALE_FACTOR = 4
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};
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/*
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***************************************************************************************
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****************** Clock Manager Private Macros and Defines ***************************
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***************************************************************************************
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*/
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/* Macros */
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#define TO_CLK_MGR_INTERNAL(clk_mgr)\
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container_of(clk_mgr, struct clk_mgr_internal, base)
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#define CTX \
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clk_mgr->base.ctx
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#define DC_LOGGER \
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clk_mgr->base.ctx->logger
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#define CLK_BASE(inst) \
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CLK_BASE_INNER(inst)
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#define CLK_SRI(reg_name, block, inst)\
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.reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
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mm ## block ## _ ## inst ## _ ## reg_name
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#define CLK_COMMON_REG_LIST_DCE_BASE() \
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.DPREFCLK_CNTL = mmDPREFCLK_CNTL, \
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.DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL
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#if defined(CONFIG_DRM_AMD_DC_SI)
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#define CLK_COMMON_REG_LIST_DCE60_BASE() \
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SR(DENTIST_DISPCLK_CNTL)
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#endif
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#define CLK_COMMON_REG_LIST_DCN_BASE() \
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SR(DENTIST_DISPCLK_CNTL)
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#define VBIOS_SMU_MSG_BOX_REG_LIST_RV() \
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.MP1_SMN_C2PMSG_91 = mmMP1_SMN_C2PMSG_91, \
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.MP1_SMN_C2PMSG_83 = mmMP1_SMN_C2PMSG_83, \
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.MP1_SMN_C2PMSG_67 = mmMP1_SMN_C2PMSG_67
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#define CLK_REG_LIST_NV10() \
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SR(DENTIST_DISPCLK_CNTL), \
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CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \
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CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0)
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#ifdef CONFIG_DRM_AMD_DC_DCN3_0
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// TODO:
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#define CLK_REG_LIST_DCN3() \
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SR(DENTIST_DISPCLK_CNTL)
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#endif
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#define CLK_SF(reg_name, field_name, post_fix)\
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.field_name = reg_name ## __ ## field_name ## post_fix
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#define CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
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CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \
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CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh)
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#if defined(CONFIG_DRM_AMD_DC_SI)
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#define CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(mask_sh) \
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CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\
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CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh)
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#endif
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#define CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \
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CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\
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CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh)
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#define CLK_MASK_SH_LIST_RV1(mask_sh) \
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CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
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CLK_SF(MP1_SMN_C2PMSG_67, CONTENT, mask_sh),\
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CLK_SF(MP1_SMN_C2PMSG_83, CONTENT, mask_sh),\
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CLK_SF(MP1_SMN_C2PMSG_91, CONTENT, mask_sh),
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#define CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh) \
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CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
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CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, mask_sh),\
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CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, mask_sh)
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#define CLK_MASK_SH_LIST_NV10(mask_sh) \
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CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
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CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_int, mask_sh),\
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CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_frac, mask_sh)
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#define CLK_REG_FIELD_LIST(type) \
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type DPREFCLK_SRC_SEL; \
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type DENTIST_DPREFCLK_WDIVIDER; \
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type DENTIST_DISPCLK_WDIVIDER; \
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type DENTIST_DISPCLK_CHG_DONE;
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/*
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***************************************************************************************
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****************** Clock Manager Private Structures ***********************************
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***************************************************************************************
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*/
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#define CLK20_REG_FIELD_LIST(type) \
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type DENTIST_DPPCLK_WDIVIDER; \
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type DENTIST_DPPCLK_CHG_DONE; \
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type FbMult_int; \
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type FbMult_frac;
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#define VBIOS_SMU_REG_FIELD_LIST(type) \
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type CONTENT;
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struct clk_mgr_shift {
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CLK_REG_FIELD_LIST(uint8_t)
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CLK20_REG_FIELD_LIST(uint8_t)
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VBIOS_SMU_REG_FIELD_LIST(uint32_t)
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};
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struct clk_mgr_mask {
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CLK_REG_FIELD_LIST(uint32_t)
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CLK20_REG_FIELD_LIST(uint32_t)
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VBIOS_SMU_REG_FIELD_LIST(uint32_t)
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};
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struct clk_mgr_registers {
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uint32_t DPREFCLK_CNTL;
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uint32_t DENTIST_DISPCLK_CNTL;
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uint32_t CLK3_CLK2_DFS_CNTL;
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uint32_t CLK3_CLK_PLL_REQ;
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#ifdef CONFIG_DRM_AMD_DC_DCN3_0
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uint32_t CLK0_CLK2_DFS_CNTL;
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uint32_t CLK0_CLK_PLL_REQ;
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#endif
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uint32_t MP1_SMN_C2PMSG_67;
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uint32_t MP1_SMN_C2PMSG_83;
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uint32_t MP1_SMN_C2PMSG_91;
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};
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enum clock_type {
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clock_type_dispclk = 1,
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clock_type_dcfclk,
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clock_type_socclk,
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clock_type_pixelclk,
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clock_type_phyclk,
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clock_type_dppclk,
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clock_type_fclk,
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clock_type_dcfdsclk,
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clock_type_dscclk,
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clock_type_uclk,
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clock_type_dramclk,
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};
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struct state_dependent_clocks {
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int display_clk_khz;
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int pixel_clk_khz;
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};
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struct clk_mgr_internal {
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struct clk_mgr base;
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int smu_ver;
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struct pp_smu_funcs *pp_smu;
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struct clk_mgr_internal_funcs *funcs;
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struct dccg *dccg;
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/*
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* For backwards compatbility with previous implementation
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* TODO: remove these after everything transitions to new pattern
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* Rationale is that clk registers change a lot across DCE versions
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* and a shared data structure doesn't really make sense.
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*/
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const struct clk_mgr_registers *regs;
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const struct clk_mgr_shift *clk_mgr_shift;
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const struct clk_mgr_mask *clk_mgr_mask;
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struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES];
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/*TODO: figure out which of the below fields should be here vs in asic specific portion */
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/* Cache the status of DFS-bypass feature*/
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bool dfs_bypass_enabled;
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/* True if the DFS-bypass feature is enabled and active. */
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bool dfs_bypass_active;
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uint32_t dfs_ref_freq_khz;
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/*
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* Cache the display clock returned by VBIOS if DFS-bypass is enabled.
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* This is basically "Crystal Frequency In KHz" (XTALIN) frequency
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*/
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int dfs_bypass_disp_clk;
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/**
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* @ss_on_dprefclk:
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*
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* True if spread spectrum is enabled on the DP ref clock.
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*/
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bool ss_on_dprefclk;
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/**
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* @xgmi_enabled:
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*
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* True if xGMI is enabled. On VG20, both audio and display clocks need
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* to be adjusted with the WAFL link's SS info if xGMI is enabled.
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*/
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bool xgmi_enabled;
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/**
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* @dprefclk_ss_percentage:
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*
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* DPREFCLK SS percentage (if down-spread enabled).
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*
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* Note that if XGMI is enabled, the SS info (percentage and divider)
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* from the WAFL link is used instead. This is decided during
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* dce_clk_mgr initialization.
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*/
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int dprefclk_ss_percentage;
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/**
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* @dprefclk_ss_divider:
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*
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* DPREFCLK SS percentage Divider (100 or 1000).
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*/
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int dprefclk_ss_divider;
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enum dm_pp_clocks_state max_clks_state;
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enum dm_pp_clocks_state cur_min_clks_state;
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bool periodic_retraining_disabled;
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unsigned int cur_phyclk_req_table[MAX_PIPES * 2];
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#ifdef CONFIG_DRM_AMD_DC_DCN3_0
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bool smu_present;
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void *wm_range_table;
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long long wm_range_table_addr;
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#endif
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};
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struct clk_mgr_internal_funcs {
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int (*set_dispclk)(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
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int (*set_dprefclk)(struct clk_mgr_internal *clk_mgr);
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};
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/*
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***************************************************************************************
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****************** Clock Manager Level Helper functions *******************************
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***************************************************************************************
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*/
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static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_clk)
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{
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return ((safe_to_lower && calc_clk < cur_clk) || calc_clk > cur_clk);
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}
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static inline bool should_update_pstate_support(bool safe_to_lower, bool calc_support, bool cur_support)
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{
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if (cur_support != calc_support) {
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if (calc_support == true && safe_to_lower)
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return true;
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else if (calc_support == false && !safe_to_lower)
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return true;
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}
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return false;
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}
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int clk_mgr_helper_get_active_display_cnt(
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struct dc *dc,
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struct dc_state *context);
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int clk_mgr_helper_get_active_plane_cnt(
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struct dc *dc,
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struct dc_state *context);
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#endif //__DAL_CLK_MGR_INTERNAL_H__
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