/*
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* Copyright 2012-16 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DAL_CLK_MGR_H__
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#define __DAL_CLK_MGR_H__
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#include "dc.h"
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#include "dm_pp_smu.h"
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#define DCN_MINIMUM_DISPCLK_Khz 100000
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#define DCN_MINIMUM_DPPCLK_Khz 100000
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/* Constants */
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#define DDR4_DRAM_WIDTH 64
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#define WM_A 0
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#define WM_B 1
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#define WM_C 2
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#define WM_D 3
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#define WM_SET_COUNT 4
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#define DCN_MINIMUM_DISPCLK_Khz 100000
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#define DCN_MINIMUM_DPPCLK_Khz 100000
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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struct dcn3_clk_internal {
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int dummy;
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/*TODO:
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uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
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uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
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uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
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uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
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uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider
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uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow
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uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
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uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
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uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
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uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
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*/
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};
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#endif
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/* Will these bw structures be ASIC specific? */
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#define MAX_NUM_DPM_LVL 8
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#define WM_SET_COUNT 4
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struct clk_limit_table_entry {
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unsigned int voltage; /* milivolts withh 2 fractional bits */
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unsigned int dcfclk_mhz;
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unsigned int fclk_mhz;
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unsigned int memclk_mhz;
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unsigned int socclk_mhz;
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#ifdef CONFIG_DRM_AMD_DC_DCN3_0
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unsigned int dtbclk_mhz;
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unsigned int dispclk_mhz;
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unsigned int dppclk_mhz;
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unsigned int phyclk_mhz;
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#endif
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};
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/* This table is contiguous */
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struct clk_limit_table {
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struct clk_limit_table_entry entries[MAX_NUM_DPM_LVL];
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unsigned int num_entries;
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};
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struct wm_range_table_entry {
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unsigned int wm_inst;
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unsigned int wm_type;
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double pstate_latency_us;
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double sr_exit_time_us;
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double sr_enter_plus_exit_time_us;
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bool valid;
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};
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#ifdef CONFIG_DRM_AMD_DC_DCN3_0
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struct nv_wm_range_entry {
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bool valid;
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struct {
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uint8_t wm_type;
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uint16_t min_dcfclk;
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uint16_t max_dcfclk;
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uint16_t min_uclk;
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uint16_t max_uclk;
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} pmfw_breakdown;
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struct {
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double pstate_latency_us;
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double sr_exit_time_us;
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double sr_enter_plus_exit_time_us;
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} dml_input;
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};
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#endif
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struct clk_log_info {
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bool enabled;
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char *pBuf;
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unsigned int bufSize;
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unsigned int *sum_chars_printed;
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};
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struct clk_state_registers_and_bypass {
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uint32_t dcfclk;
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uint32_t dcf_deep_sleep_divider;
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uint32_t dcf_deep_sleep_allow;
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uint32_t dprefclk;
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uint32_t dispclk;
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uint32_t dppclk;
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uint32_t dppclk_bypass;
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uint32_t dcfclk_bypass;
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uint32_t dprefclk_bypass;
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uint32_t dispclk_bypass;
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};
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struct rv1_clk_internal {
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uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk
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uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider
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uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow
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uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk
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uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk
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uint32_t CLK0_CLK8_BYPASS_CNTL; //dcfclk bypass
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uint32_t CLK0_CLK10_BYPASS_CNTL; //dprefclk bypass
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uint32_t CLK0_CLK11_BYPASS_CNTL; //dispclk bypass
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};
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struct rn_clk_internal {
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uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
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uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
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uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
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uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
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uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider
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uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow
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uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
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uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
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uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
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uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
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};
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/* For dtn logging and debugging */
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struct clk_state_registers {
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uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk
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uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider
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uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow
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uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk
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uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk
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};
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/* TODO: combine this with the above */
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struct clk_bypass {
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uint32_t dcfclk_bypass;
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uint32_t dispclk_pypass;
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uint32_t dprefclk_bypass;
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};
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/*
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* This table is not contiguous, can have holes, each
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* entry correspond to one set of WM. For example if
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* we have 2 DPM and LPDDR, we will WM set A, B and
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* D occupied, C will be emptry.
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*/
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struct wm_table {
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#ifdef CONFIG_DRM_AMD_DC_DCN3_0
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union {
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struct nv_wm_range_entry nv_entries[WM_SET_COUNT];
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#endif
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struct wm_range_table_entry entries[WM_SET_COUNT];
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#ifdef CONFIG_DRM_AMD_DC_DCN3_0
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};
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#endif
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};
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struct dummy_pstate_entry {
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unsigned int dram_speed_mts;
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unsigned int dummy_pstate_latency_us;
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};
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struct clk_bw_params {
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unsigned int vram_type;
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unsigned int num_channels;
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struct clk_limit_table clk_table;
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struct wm_table wm_table;
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struct dummy_pstate_entry dummy_pstate_table[4];
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};
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/* Public interfaces */
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struct clk_states {
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uint32_t dprefclk_khz;
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};
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struct clk_mgr_funcs {
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/*
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* This function should set new clocks based on the input "safe_to_lower".
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* If safe_to_lower == false, then only clocks which are to be increased
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* should changed.
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* If safe_to_lower == true, then only clocks which are to be decreased
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* should be changed.
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*/
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void (*update_clocks)(struct clk_mgr *clk_mgr,
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struct dc_state *context,
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bool safe_to_lower);
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int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr);
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void (*set_low_power_state)(struct clk_mgr *clk_mgr);
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void (*init_clocks)(struct clk_mgr *clk_mgr);
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void (*enable_pme_wa) (struct clk_mgr *clk_mgr);
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void (*get_clock)(struct clk_mgr *clk_mgr,
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struct dc_state *context,
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enum dc_clock_type clock_type,
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struct dc_clock_config *clock_cfg);
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bool (*are_clock_states_equal) (struct dc_clocks *a,
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struct dc_clocks *b);
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void (*notify_wm_ranges)(struct clk_mgr *clk_mgr);
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/* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
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void (*notify_link_rate_change)(struct clk_mgr *clk_mgr, struct dc_link *link);
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#ifdef CONFIG_DRM_AMD_DC_DCN3_0
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/*
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* Send message to PMFW to set hard min memclk frequency
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* When current_mode = false, set DPM0
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* When current_mode = true, set required clock for current mode
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*/
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void (*set_hard_min_memclk)(struct clk_mgr *clk_mgr, bool current_mode);
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/* Send message to PMFW to set hard max memclk frequency to highest DPM */
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void (*set_hard_max_memclk)(struct clk_mgr *clk_mgr);
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/* Get current memclk states from PMFW, update relevant structures */
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void (*get_memclk_states_from_smu)(struct clk_mgr *clk_mgr);
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#endif
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};
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struct clk_mgr {
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struct dc_context *ctx;
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struct clk_mgr_funcs *funcs;
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struct dc_clocks clks;
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bool psr_allow_active_cache;
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#ifdef CONFIG_DRM_AMD_DC_DCN3_0
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bool force_smu_not_present;
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#endif
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int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes
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int dentist_vco_freq_khz;
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struct clk_state_registers_and_bypass boot_snapshot;
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struct clk_bw_params *bw_params;
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struct pp_smu_wm_range_sets ranges;
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};
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/* forward declarations */
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struct dccg;
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struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg);
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void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr);
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void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr);
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void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr);
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#endif /* __DAL_CLK_MGR_H__ */
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