/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef DAL_DC_DCN30_CLK_MGR_SMU_MSG_H_
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#define DAL_DC_DCN30_CLK_MGR_SMU_MSG_H_
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#include "core_types.h"
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#define SMU11_DRIVER_IF_VERSION 0x1F
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typedef enum {
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PPCLK_GFXCLK = 0,
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PPCLK_SOCCLK,
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PPCLK_UCLK,
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PPCLK_FCLK,
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PPCLK_DCLK_0,
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PPCLK_VCLK_0,
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PPCLK_DCLK_1,
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PPCLK_VCLK_1,
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PPCLK_DCEFCLK,
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PPCLK_DISPCLK,
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PPCLK_PIXCLK,
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PPCLK_PHYCLK,
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PPCLK_DTBCLK,
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PPCLK_COUNT,
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} PPCLK_e;
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typedef struct {
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uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz)
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uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz)
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uint16_t MinUclk;
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uint16_t MaxUclk;
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uint8_t WmSetting;
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uint8_t Flags;
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uint8_t Padding[2];
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} WatermarkRowGeneric_t;
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#define NUM_WM_RANGES 4
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typedef enum {
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WM_SOCCLK = 0,
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WM_DCEFCLK,
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WM_COUNT,
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} WM_CLOCK_e;
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typedef enum {
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WATERMARKS_CLOCK_RANGE = 0,
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WATERMARKS_DUMMY_PSTATE,
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WATERMARKS_COUNT,
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} WATERMARKS_FLAGS_e;
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typedef struct {
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// Watermarks
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WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
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} Watermarks_t;
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typedef struct {
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Watermarks_t Watermarks;
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uint32_t MmHubPadding[8]; // SMU internal use
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} WatermarksExternal_t;
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#define TABLE_WATERMARKS 1
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struct clk_mgr_internal;
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bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input);
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bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version);
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bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr);
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bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr);
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void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
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void dcn30_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
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void dcn30_smu_transfer_wm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
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void dcn30_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
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unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint16_t freq_mhz);
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unsigned int dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint16_t freq_mhz);
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unsigned int dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint8_t dpm_level);
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unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk);
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void dcn30_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz);
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void dcn30_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays);
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void dcn30_smu_set_external_client_df_cstate_allow(struct clk_mgr_internal *clk_mgr, bool enable);
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void dcn30_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr);
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#endif /* DAL_DC_DCN30_CLK_MGR_SMU_MSG_H_ */
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