/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include <linux/delay.h>
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#include "dcn30_clk_mgr_smu_msg.h"
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#include "clk_mgr_internal.h"
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#include "reg_helper.h"
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#include "dalsmc.h"
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#define mmDAL_MSG_REG 0x1628A
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#define mmDAL_ARG_REG 0x16273
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#define mmDAL_RESP_REG 0x16274
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#define REG(reg_name) \
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mm ## reg_name
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#include "logger_types.h"
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#undef DC_LOGGER
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#define DC_LOGGER \
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CTX->logger
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#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
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/*
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* Function to be used instead of REG_WAIT macro because the wait ends when
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* the register is NOT EQUAL to zero, and because the translation in msg_if.h
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* won't work with REG_WAIT.
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*/
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static uint32_t dcn30_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
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{
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uint32_t reg = 0;
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do {
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reg = REG_READ(DAL_RESP_REG);
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if (reg)
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break;
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if (delay_us >= 1000)
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msleep(delay_us/1000);
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else if (delay_us > 0)
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udelay(delay_us);
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} while (max_retries--);
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/* handle DALSMC_Result_CmdRejectedBusy? */
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/* Log? */
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return reg;
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}
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static bool dcn30_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)
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{
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/* Wait for response register to be ready */
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dcn30_smu_wait_for_response(clk_mgr, 10, 200000);
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/* Clear response register */
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REG_WRITE(DAL_RESP_REG, 0);
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/* Set the parameter register for the SMU message */
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REG_WRITE(DAL_ARG_REG, param_in);
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/* Trigger the message transaction by writing the message ID */
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REG_WRITE(DAL_MSG_REG, msg_id);
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/* Wait for response */
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if (dcn30_smu_wait_for_response(clk_mgr, 10, 200000) == DALSMC_Result_OK) {
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if (param_out)
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*param_out = REG_READ(DAL_ARG_REG);
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return true;
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}
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return false;
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}
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/* Test message should return input + 1 */
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bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input)
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{
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uint32_t response = 0;
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smu_print("SMU Test message: %d\n", input);
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if (dcn30_smu_send_msg_with_param(clk_mgr,
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DALSMC_MSG_TestMessage, input, &response))
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if (response == input + 1)
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return true;
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return false;
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}
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bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version)
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{
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smu_print("SMU Get SMU version\n");
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if (dcn30_smu_send_msg_with_param(clk_mgr,
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DALSMC_MSG_GetSmuVersion, 0, version)) {
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smu_print("SMU version: %d\n", *version);
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return true;
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}
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return false;
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}
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/* Message output should match SMU11_DRIVER_IF_VERSION in smu11_driver_if.h */
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bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr)
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{
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uint32_t response = 0;
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smu_print("SMU Check driver if version\n");
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if (dcn30_smu_send_msg_with_param(clk_mgr,
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DALSMC_MSG_GetDriverIfVersion, 0, &response)) {
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smu_print("SMU driver if version: %d\n", response);
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if (response == SMU11_DRIVER_IF_VERSION)
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return true;
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}
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return false;
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}
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/* Message output should match DALSMC_VERSION in dalsmc.h */
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bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr)
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{
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uint32_t response = 0;
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smu_print("SMU Check msg header version\n");
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if (dcn30_smu_send_msg_with_param(clk_mgr,
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DALSMC_MSG_GetMsgHeaderVersion, 0, &response)) {
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smu_print("SMU msg header version: %d\n", response);
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if (response == DALSMC_VERSION)
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return true;
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}
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return false;
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}
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void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)
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{
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smu_print("SMU Set DRAM addr high: %d\n", addr_high);
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dcn30_smu_send_msg_with_param(clk_mgr,
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DALSMC_MSG_SetDalDramAddrHigh, addr_high, NULL);
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}
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void dcn30_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)
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{
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smu_print("SMU Set DRAM addr low: %d\n", addr_low);
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dcn30_smu_send_msg_with_param(clk_mgr,
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DALSMC_MSG_SetDalDramAddrLow, addr_low, NULL);
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}
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void dcn30_smu_transfer_wm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)
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{
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smu_print("SMU Transfer WM table SMU 2 DRAM\n");
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dcn30_smu_send_msg_with_param(clk_mgr,
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DALSMC_MSG_TransferTableSmu2Dram, TABLE_WATERMARKS, NULL);
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}
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void dcn30_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
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{
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smu_print("SMU Transfer WM table DRAM 2 SMU\n");
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dcn30_smu_send_msg_with_param(clk_mgr,
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DALSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS, NULL);
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}
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/* Returns the actual frequency that was set in MHz, 0 on failure */
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unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint16_t freq_mhz)
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{
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uint32_t response = 0;
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/* bits 23:16 for clock type, lower 16 bits for frequency in MHz */
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uint32_t param = (clk << 16) | freq_mhz;
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smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz);
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dcn30_smu_send_msg_with_param(clk_mgr,
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DALSMC_MSG_SetHardMinByFreq, param, &response);
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smu_print("SMU Frequency set = %d MHz\n", response);
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return response;
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}
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/* Returns the actual frequency that was set in MHz, 0 on failure */
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unsigned int dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint16_t freq_mhz)
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{
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uint32_t response = 0;
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/* bits 23:16 for clock type, lower 16 bits for frequency in MHz */
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uint32_t param = (clk << 16) | freq_mhz;
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smu_print("SMU Set hard max by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz);
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dcn30_smu_send_msg_with_param(clk_mgr,
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DALSMC_MSG_SetHardMaxByFreq, param, &response);
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smu_print("SMU Frequency set = %d MHz\n", response);
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return response;
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}
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/*
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* Frequency in MHz returned in lower 16 bits for valid DPM level
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*
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* Call with dpm_level = 0xFF to query features, return value will be:
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* Bits 7:0 - number of DPM levels
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* Bit 28 - 1 = auto DPM on
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* Bit 29 - 1 = sweep DPM on
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* Bit 30 - 1 = forced DPM on
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* Bit 31 - 0 = discrete, 1 = fine-grained
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*
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* With fine-grained DPM, only min and max frequencies will be reported
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*
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* Returns 0 on failure
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*/
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unsigned int dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint8_t dpm_level)
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{
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uint32_t response = 0;
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/* bits 23:16 for clock type, lower 8 bits for DPM level */
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uint32_t param = (clk << 16) | dpm_level;
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smu_print("SMU Get dpm freq by index: clk = %d, dpm_level = %d\n", clk, dpm_level);
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dcn30_smu_send_msg_with_param(clk_mgr,
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DALSMC_MSG_GetDpmFreqByIndex, param, &response);
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smu_print("SMU dpm freq: %d MHz\n", response);
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return response;
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}
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/* Returns the max DPM frequency in DC mode in MHz, 0 on failure */
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unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk)
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{
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uint32_t response = 0;
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/* bits 23:16 for clock type */
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uint32_t param = clk << 16;
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smu_print("SMU Get DC mode max DPM freq: clk = %d\n", clk);
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dcn30_smu_send_msg_with_param(clk_mgr,
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DALSMC_MSG_GetDcModeMaxDpmFreq, param, &response);
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smu_print("SMU DC mode max DMP freq: %d MHz\n", response);
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return response;
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}
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void dcn30_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz)
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{
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smu_print("SMU Set min deep sleep dcef clk: freq_mhz = %d MHz\n", freq_mhz);
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dcn30_smu_send_msg_with_param(clk_mgr,
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DALSMC_MSG_SetMinDeepSleepDcefclk, freq_mhz, NULL);
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}
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void dcn30_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays)
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{
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smu_print("SMU Set num of displays: num_displays = %d\n", num_displays);
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dcn30_smu_send_msg_with_param(clk_mgr,
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DALSMC_MSG_NumOfDisplays, num_displays, NULL);
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}
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void dcn30_smu_set_external_client_df_cstate_allow(struct clk_mgr_internal *clk_mgr, bool enable)
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{
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smu_print("SMU Set external client df cstate allow: enable = %d\n", enable);
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dcn30_smu_send_msg_with_param(clk_mgr,
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DALSMC_MSG_SetExternalClientDfCstateAllow, enable ? 1 : 0, NULL);
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}
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void dcn30_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr)
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{
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smu_print("SMU Set PME workaround\n");
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dcn30_smu_send_msg_with_param(clk_mgr,
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DALSMC_MSG_BacoAudioD3PME, 0, NULL);
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}
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