/*
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* Copyright 2012-16 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "core_types.h"
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#include "clk_mgr_internal.h"
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#include "reg_helper.h"
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#include <linux/delay.h>
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#include "renoir_ip_offset.h"
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#include "mp/mp_12_0_0_offset.h"
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#include "mp/mp_12_0_0_sh_mask.h"
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#define REG(reg_name) \
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(MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
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#define FN(reg_name, field) \
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FD(reg_name##__##field)
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#define VBIOSSMC_MSG_TestMessage 0x1
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#define VBIOSSMC_MSG_GetSmuVersion 0x2
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#define VBIOSSMC_MSG_PowerUpGfx 0x3
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#define VBIOSSMC_MSG_SetDispclkFreq 0x4
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#define VBIOSSMC_MSG_SetDprefclkFreq 0x5
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#define VBIOSSMC_MSG_PowerDownGfx 0x6
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#define VBIOSSMC_MSG_SetDppclkFreq 0x7
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#define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x8
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#define VBIOSSMC_MSG_SetMinDeepSleepDcfclk 0x9
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#define VBIOSSMC_MSG_SetPhyclkVoltageByFreq 0xA
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#define VBIOSSMC_MSG_GetFclkFrequency 0xB
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#define VBIOSSMC_MSG_SetDisplayCount 0xC
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#define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0xD
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#define VBIOSSMC_MSG_UpdatePmeRestore 0xE
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#define VBIOSSMC_MSG_IsPeriodicRetrainingDisabled 0xF
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#define VBIOSSMC_Status_BUSY 0x0
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#define VBIOSSMC_Result_OK 0x1
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#define VBIOSSMC_Result_Failed 0xFF
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#define VBIOSSMC_Result_UnknownCmd 0xFE
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#define VBIOSSMC_Result_CmdRejectedPrereq 0xFD
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#define VBIOSSMC_Result_CmdRejectedBusy 0xFC
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/*
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* Function to be used instead of REG_WAIT macro because the wait ends when
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* the register is NOT EQUAL to zero, and because the translation in msg_if.h
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* won't work with REG_WAIT.
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*/
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static uint32_t rn_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
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{
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uint32_t res_val = VBIOSSMC_Status_BUSY;
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do {
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res_val = REG_READ(MP1_SMN_C2PMSG_91);
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if (res_val != VBIOSSMC_Status_BUSY)
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break;
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if (delay_us >= 1000)
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msleep(delay_us/1000);
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else if (delay_us > 0)
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udelay(delay_us);
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} while (max_retries--);
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return res_val;
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}
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int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigned int param)
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{
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uint32_t result;
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/* First clear response register */
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REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
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/* Set the parameter register for the SMU message, unit is Mhz */
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REG_WRITE(MP1_SMN_C2PMSG_83, param);
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/* Trigger the message transaction by writing the message ID */
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REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
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result = rn_smu_wait_for_response(clk_mgr, 10, 1000);
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ASSERT(result == VBIOSSMC_Result_OK || result == VBIOSSMC_Result_UnknownCmd);
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/* Actual dispclk set is returned in the parameter register */
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return REG_READ(MP1_SMN_C2PMSG_83);
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}
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int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)
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{
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return rn_vbios_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_GetSmuVersion,
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0);
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}
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int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
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{
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int actual_dispclk_set_mhz = -1;
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struct dc *dc = clk_mgr->base.ctx->dc;
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struct dmcu *dmcu = dc->res_pool->dmcu;
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/* Unit of SMU msg parameter is Mhz */
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actual_dispclk_set_mhz = rn_vbios_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_SetDispclkFreq,
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requested_dispclk_khz / 1000);
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if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
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if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
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if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz)
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dmcu->funcs->set_psr_wait_loop(dmcu,
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actual_dispclk_set_mhz / 7);
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}
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}
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return actual_dispclk_set_mhz * 1000;
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}
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int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
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{
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int actual_dprefclk_set_mhz = -1;
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actual_dprefclk_set_mhz = rn_vbios_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_SetDprefclkFreq,
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clk_mgr->base.dprefclk_khz / 1000);
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/* TODO: add code for programing DP DTO, currently this is down by command table */
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return actual_dprefclk_set_mhz * 1000;
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}
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int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)
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{
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int actual_dcfclk_set_mhz = -1;
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if (clk_mgr->smu_ver < 0x370c00)
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return actual_dcfclk_set_mhz;
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actual_dcfclk_set_mhz = rn_vbios_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
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requested_dcfclk_khz / 1000);
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return actual_dcfclk_set_mhz * 1000;
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}
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int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)
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{
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int actual_min_ds_dcfclk_mhz = -1;
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if (clk_mgr->smu_ver < 0x370c00)
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return actual_min_ds_dcfclk_mhz;
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actual_min_ds_dcfclk_mhz = rn_vbios_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_SetMinDeepSleepDcfclk,
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requested_min_ds_dcfclk_khz / 1000);
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return actual_min_ds_dcfclk_mhz * 1000;
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}
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void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz)
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{
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rn_vbios_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_SetPhyclkVoltageByFreq,
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requested_phyclk_khz / 1000);
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}
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int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
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{
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int actual_dppclk_set_mhz = -1;
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actual_dppclk_set_mhz = rn_vbios_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_SetDppclkFreq,
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requested_dpp_khz / 1000);
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return actual_dppclk_set_mhz * 1000;
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}
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void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, enum dcn_pwr_state state)
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{
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int disp_count;
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if (state == DCN_PWR_STATE_LOW_POWER)
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disp_count = 0;
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else
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disp_count = 1;
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rn_vbios_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_SetDisplayCount,
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disp_count);
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}
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void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
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{
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rn_vbios_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown,
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enable);
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}
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void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)
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{
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rn_vbios_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_UpdatePmeRestore,
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0);
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}
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int rn_vbios_smu_is_periodic_retraining_disabled(struct clk_mgr_internal *clk_mgr)
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{
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return rn_vbios_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_IsPeriodicRetrainingDisabled,
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0);
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}
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