/*
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* Copyright 2012-16 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "core_types.h"
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#include "clk_mgr_internal.h"
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#include "reg_helper.h"
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#include <linux/delay.h>
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#define MAX_INSTANCE 5
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#define MAX_SEGMENT 5
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struct IP_BASE_INSTANCE {
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unsigned int segment[MAX_SEGMENT];
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};
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struct IP_BASE {
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struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
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};
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static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } } } };
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#define mmMP1_SMN_C2PMSG_91 0x29B
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#define mmMP1_SMN_C2PMSG_83 0x293
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#define mmMP1_SMN_C2PMSG_67 0x283
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#define mmMP1_SMN_C2PMSG_91_BASE_IDX 0
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#define mmMP1_SMN_C2PMSG_83_BASE_IDX 0
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#define mmMP1_SMN_C2PMSG_67_BASE_IDX 0
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#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xffffffffL
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#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xffffffffL
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#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xffffffffL
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#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x00000000
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#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x00000000
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#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x00000000
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#define REG(reg_name) \
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(MP1_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
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#define FN(reg_name, field) \
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FD(reg_name##__##field)
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#define VBIOSSMC_MSG_SetDispclkFreq 0x4
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#define VBIOSSMC_MSG_SetDprefclkFreq 0x5
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#define VBIOSSMC_Status_BUSY 0x0
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#define VBIOSSMC_Result_OK 0x1
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#define VBIOSSMC_Result_Failed 0xFF
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#define VBIOSSMC_Result_UnknownCmd 0xFE
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#define VBIOSSMC_Result_CmdRejectedPrereq 0xFD
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#define VBIOSSMC_Result_CmdRejectedBusy 0xFC
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/*
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* Function to be used instead of REG_WAIT macro because the wait ends when
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* the register is NOT EQUAL to zero, and because the translation in msg_if.h
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* won't work with REG_WAIT.
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*/
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static uint32_t rv1_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
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{
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uint32_t res_val = VBIOSSMC_Status_BUSY;
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do {
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res_val = REG_READ(MP1_SMN_C2PMSG_91);
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if (res_val != VBIOSSMC_Status_BUSY)
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break;
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if (delay_us >= 1000)
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msleep(delay_us/1000);
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else if (delay_us > 0)
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udelay(delay_us);
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} while (max_retries--);
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return res_val;
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}
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int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigned int param)
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{
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uint32_t result;
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/* First clear response register */
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REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
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/* Set the parameter register for the SMU message, unit is Mhz */
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REG_WRITE(MP1_SMN_C2PMSG_83, param);
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/* Trigger the message transaction by writing the message ID */
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REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
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result = rv1_smu_wait_for_response(clk_mgr, 10, 1000);
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ASSERT(result == VBIOSSMC_Result_OK);
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/* Actual dispclk set is returned in the parameter register */
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return REG_READ(MP1_SMN_C2PMSG_83);
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}
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int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
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{
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int actual_dispclk_set_mhz = -1;
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struct dc *dc = clk_mgr->base.ctx->dc;
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struct dmcu *dmcu = dc->res_pool->dmcu;
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/* Unit of SMU msg parameter is Mhz */
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actual_dispclk_set_mhz = rv1_vbios_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_SetDispclkFreq,
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requested_dispclk_khz / 1000);
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if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
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if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
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if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz)
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dmcu->funcs->set_psr_wait_loop(dmcu,
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actual_dispclk_set_mhz / 7);
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}
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}
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return actual_dispclk_set_mhz * 1000;
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}
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int rv1_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
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{
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int actual_dprefclk_set_mhz = -1;
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actual_dprefclk_set_mhz = rv1_vbios_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_SetDprefclkFreq,
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clk_mgr->base.dprefclk_khz / 1000);
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/* TODO: add code for programing DP DTO, currently this is down by command table */
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return actual_dprefclk_set_mhz * 1000;
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}
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