/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include <linux/slab.h>
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#include "reg_helper.h"
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#include "core_types.h"
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#include "clk_mgr_internal.h"
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#include "rv1_clk_mgr.h"
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#include "dce100/dce_clk_mgr.h"
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#include "dce112/dce112_clk_mgr.h"
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#include "rv1_clk_mgr_vbios_smu.h"
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#include "rv1_clk_mgr_clk.h"
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void rv1_init_clocks(struct clk_mgr *clk_mgr)
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{
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memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
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}
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static int rv1_determine_dppclk_threshold(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks)
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{
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bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
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bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz;
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int disp_clk_threshold = new_clocks->max_supported_dppclk_khz;
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bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz;
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/* increase clock, looking for div is 0 for current, request div is 1*/
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if (dispclk_increase) {
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/* already divided by 2, no need to reach target clk with 2 steps*/
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if (cur_dpp_div)
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return new_clocks->dispclk_khz;
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/* request disp clk is lower than maximum supported dpp clk,
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* no need to reach target clk with two steps.
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*/
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if (new_clocks->dispclk_khz <= disp_clk_threshold)
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return new_clocks->dispclk_khz;
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/* target dpp clk not request divided by 2, still within threshold */
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if (!request_dpp_div)
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return new_clocks->dispclk_khz;
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} else {
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/* decrease clock, looking for current dppclk divided by 2,
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* request dppclk not divided by 2.
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*/
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/* current dpp clk not divided by 2, no need to ramp*/
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if (!cur_dpp_div)
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return new_clocks->dispclk_khz;
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/* current disp clk is lower than current maximum dpp clk,
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* no need to ramp
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*/
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if (clk_mgr->base.clks.dispclk_khz <= disp_clk_threshold)
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return new_clocks->dispclk_khz;
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/* request dpp clk need to be divided by 2 */
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if (request_dpp_div)
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return new_clocks->dispclk_khz;
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}
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return disp_clk_threshold;
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}
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static void ramp_up_dispclk_with_dpp(
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struct clk_mgr_internal *clk_mgr,
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struct dc *dc,
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struct dc_clocks *new_clocks,
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bool safe_to_lower)
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{
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int i;
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int dispclk_to_dpp_threshold = rv1_determine_dppclk_threshold(clk_mgr, new_clocks);
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bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
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/* this function is to change dispclk, dppclk and dprefclk according to
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* bandwidth requirement. Its call stack is rv1_update_clocks -->
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* update_clocks --> dcn10_prepare_bandwidth / dcn10_optimize_bandwidth
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* --> prepare_bandwidth / optimize_bandwidth. before change dcn hw,
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* prepare_bandwidth will be called first to allow enough clock,
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* watermark for change, after end of dcn hw change, optimize_bandwidth
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* is executed to lower clock to save power for new dcn hw settings.
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*
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* below is sequence of commit_planes_for_stream:
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*
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* step 1: prepare_bandwidth - raise clock to have enough bandwidth
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* step 2: lock_doublebuffer_enable
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* step 3: pipe_control_lock(true) - make dchubp register change will
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* not take effect right way
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* step 4: apply_ctx_for_surface - program dchubp
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* step 5: pipe_control_lock(false) - dchubp register change take effect
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* step 6: optimize_bandwidth --> dc_post_update_surfaces_to_stream
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* for full_date, optimize clock to save power
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*
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* at end of step 1, dcn clocks (dprefclk, dispclk, dppclk) may be
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* changed for new dchubp configuration. but real dcn hub dchubps are
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* still running with old configuration until end of step 5. this need
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* clocks settings at step 1 should not less than that before step 1.
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* this is checked by two conditions: 1. if (should_set_clock(safe_to_lower
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* , new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) ||
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* new_clocks->dispclk_khz == clk_mgr_base->clks.dispclk_khz)
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* 2. request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz
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*
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* the second condition is based on new dchubp configuration. dppclk
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* for new dchubp may be different from dppclk before step 1.
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* for example, before step 1, dchubps are as below:
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* pipe 0: recout=(0,40,1920,980) viewport=(0,0,1920,979)
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* pipe 1: recout=(0,0,1920,1080) viewport=(0,0,1920,1080)
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* for dppclk for pipe0 need dppclk = dispclk
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*
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* new dchubp pipe split configuration:
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* pipe 0: recout=(0,0,960,1080) viewport=(0,0,960,1080)
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* pipe 1: recout=(960,0,960,1080) viewport=(960,0,960,1080)
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* dppclk only needs dppclk = dispclk /2.
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*
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* dispclk, dppclk are not lock by otg master lock. they take effect
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* after step 1. during this transition, dispclk are the same, but
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* dppclk is changed to half of previous clock for old dchubp
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* configuration between step 1 and step 6. This may cause p-state
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* warning intermittently.
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*
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* for new_clocks->dispclk_khz == clk_mgr_base->clks.dispclk_khz, we
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* need make sure dppclk are not changed to less between step 1 and 6.
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* for new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz,
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* new display clock is raised, but we do not know ratio of
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* new_clocks->dispclk_khz and clk_mgr_base->clks.dispclk_khz,
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* new_clocks->dispclk_khz /2 does not guarantee equal or higher than
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* old dppclk. we could ignore power saving different between
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* dppclk = displck and dppclk = dispclk / 2 between step 1 and step 6.
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* as long as safe_to_lower = false, set dpclk = dispclk to simplify
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* condition check.
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* todo: review this change for other asic.
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**/
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if (!safe_to_lower)
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request_dpp_div = false;
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/* set disp clk to dpp clk threshold */
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clk_mgr->funcs->set_dispclk(clk_mgr, dispclk_to_dpp_threshold);
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clk_mgr->funcs->set_dprefclk(clk_mgr);
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/* update request dpp clk division option */
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
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if (!pipe_ctx->plane_state)
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continue;
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pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control(
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pipe_ctx->plane_res.dpp,
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request_dpp_div,
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true);
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}
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/* If target clk not same as dppclk threshold, set to target clock */
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if (dispclk_to_dpp_threshold != new_clocks->dispclk_khz) {
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clk_mgr->funcs->set_dispclk(clk_mgr, new_clocks->dispclk_khz);
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clk_mgr->funcs->set_dprefclk(clk_mgr);
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}
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clk_mgr->base.clks.dispclk_khz = new_clocks->dispclk_khz;
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clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;
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clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz;
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}
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static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
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struct dc_state *context,
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bool safe_to_lower)
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{
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struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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struct dc *dc = clk_mgr_base->ctx->dc;
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struct dc_debug_options *debug = &dc->debug;
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struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
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struct pp_smu_funcs_rv *pp_smu = NULL;
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bool send_request_to_increase = false;
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bool send_request_to_lower = false;
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int display_count;
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bool enter_display_off = false;
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ASSERT(clk_mgr->pp_smu);
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if (dc->work_arounds.skip_clock_update)
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return;
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pp_smu = &clk_mgr->pp_smu->rv_funcs;
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display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
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if (display_count == 0)
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enter_display_off = true;
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if (enter_display_off == safe_to_lower) {
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/*
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* Notify SMU active displays
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* if function pointer not set up, this message is
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* sent as part of pplib_apply_display_requirements.
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*/
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if (pp_smu->set_display_count)
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pp_smu->set_display_count(&pp_smu->pp_smu, display_count);
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}
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if (new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz
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|| new_clocks->phyclk_khz > clk_mgr_base->clks.phyclk_khz
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|| new_clocks->fclk_khz > clk_mgr_base->clks.fclk_khz
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|| new_clocks->dcfclk_khz > clk_mgr_base->clks.dcfclk_khz)
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send_request_to_increase = true;
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if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
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clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
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send_request_to_lower = true;
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}
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// F Clock
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if (debug->force_fclk_khz != 0)
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new_clocks->fclk_khz = debug->force_fclk_khz;
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if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, clk_mgr_base->clks.fclk_khz)) {
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clk_mgr_base->clks.fclk_khz = new_clocks->fclk_khz;
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send_request_to_lower = true;
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}
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//DCF Clock
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if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
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clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
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send_request_to_lower = true;
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}
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if (should_set_clock(safe_to_lower,
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new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
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clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
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send_request_to_lower = true;
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}
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/* make sure dcf clk is before dpp clk to
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* make sure we have enough voltage to run dpp clk
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*/
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if (send_request_to_increase) {
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/*use dcfclk to request voltage*/
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if (pp_smu->set_hard_min_fclk_by_freq &&
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pp_smu->set_hard_min_dcfclk_by_freq &&
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pp_smu->set_min_deep_sleep_dcfclk) {
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pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, new_clocks->fclk_khz / 1000);
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pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, new_clocks->dcfclk_khz / 1000);
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pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
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}
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}
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/* dcn1 dppclk is tied to dispclk */
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/* program dispclk on = as a w/a for sleep resume clock ramping issues */
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if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)
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|| new_clocks->dispclk_khz == clk_mgr_base->clks.dispclk_khz) {
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ramp_up_dispclk_with_dpp(clk_mgr, dc, new_clocks, safe_to_lower);
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clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
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send_request_to_lower = true;
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}
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if (!send_request_to_increase && send_request_to_lower) {
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/*use dcfclk to request voltage*/
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if (pp_smu->set_hard_min_fclk_by_freq &&
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pp_smu->set_hard_min_dcfclk_by_freq &&
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pp_smu->set_min_deep_sleep_dcfclk) {
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pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, new_clocks->fclk_khz / 1000);
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pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, new_clocks->dcfclk_khz / 1000);
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pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
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}
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}
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}
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static void rv1_enable_pme_wa(struct clk_mgr *clk_mgr_base)
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{
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struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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struct pp_smu_funcs_rv *pp_smu = NULL;
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if (clk_mgr->pp_smu) {
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pp_smu = &clk_mgr->pp_smu->rv_funcs;
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if (pp_smu->set_pme_wa_enable)
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pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);
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}
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}
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static struct clk_mgr_funcs rv1_clk_funcs = {
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.init_clocks = rv1_init_clocks,
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.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
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.update_clocks = rv1_update_clocks,
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.enable_pme_wa = rv1_enable_pme_wa,
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};
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static struct clk_mgr_internal_funcs rv1_clk_internal_funcs = {
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.set_dispclk = rv1_vbios_smu_set_dispclk,
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.set_dprefclk = dce112_set_dprefclk
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};
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void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu)
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{
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struct dc_debug_options *debug = &ctx->dc->debug;
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struct dc_bios *bp = ctx->dc_bios;
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clk_mgr->base.ctx = ctx;
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clk_mgr->pp_smu = pp_smu;
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clk_mgr->base.funcs = &rv1_clk_funcs;
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clk_mgr->funcs = &rv1_clk_internal_funcs;
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clk_mgr->dfs_bypass_disp_clk = 0;
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clk_mgr->dprefclk_ss_percentage = 0;
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clk_mgr->dprefclk_ss_divider = 1000;
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clk_mgr->ss_on_dprefclk = false;
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clk_mgr->base.dprefclk_khz = 600000;
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if (bp->integrated_info)
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clk_mgr->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
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if (bp->fw_info_valid && clk_mgr->base.dentist_vco_freq_khz == 0) {
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clk_mgr->base.dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
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if (clk_mgr->base.dentist_vco_freq_khz == 0)
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clk_mgr->base.dentist_vco_freq_khz = 3600000;
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}
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if (!debug->disable_dfs_bypass && bp->integrated_info)
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if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
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clk_mgr->dfs_bypass_enabled = true;
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dce_clock_read_ss_info(clk_mgr);
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}
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