/*
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* Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dccg.h"
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#include "clk_mgr_internal.h"
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#include "dce100/dce_clk_mgr.h"
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#include "dce110/dce110_clk_mgr.h"
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#include "dce60_clk_mgr.h"
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#include "reg_helper.h"
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#include "dmcu.h"
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#include "core_types.h"
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#include "dal_asic_id.h"
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/*
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* Currently the register shifts and masks in this file are used for dce60
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* which has no DPREFCLK_CNTL register
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* TODO: remove this when DENTIST_DISPCLK_CNTL
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* is moved to dccg, where it belongs
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*/
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#include "dce/dce_6_0_d.h"
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#include "dce/dce_6_0_sh_mask.h"
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#define REG(reg) \
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(clk_mgr->regs->reg)
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#undef FN
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#define FN(reg_name, field_name) \
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clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
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/* set register offset */
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#define SR(reg_name)\
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.reg_name = mm ## reg_name
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static const struct clk_mgr_registers disp_clk_regs = {
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CLK_COMMON_REG_LIST_DCE60_BASE()
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};
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static const struct clk_mgr_shift disp_clk_shift = {
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CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(__SHIFT)
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};
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static const struct clk_mgr_mask disp_clk_mask = {
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CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(_MASK)
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};
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/* Max clock values for each state indexed by "enum clocks_state": */
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static const struct state_dependent_clocks dce60_max_clks_by_state[] = {
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/* ClocksStateInvalid - should not be used */
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{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
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/* ClocksStateUltraLow - not expected to be used for DCE 6.0 */
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{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
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/* ClocksStateLow */
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{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
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/* ClocksStateNominal */
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{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
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/* ClocksStatePerformance */
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{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
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static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
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{
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struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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int dprefclk_wdivider;
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int dp_ref_clk_khz;
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int target_div;
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/* DCE6 has no DPREFCLK_CNTL to read DP Reference Clock source */
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/* Read the mmDENTIST_DISPCLK_CNTL to get the currently
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* programmed DID DENTIST_DPREFCLK_WDIVIDER*/
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REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider);
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/* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/
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target_div = dentist_get_divider_from_did(dprefclk_wdivider);
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/* Calculate the current DFS clock, in kHz.*/
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dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
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* clk_mgr->base.dentist_vco_freq_khz) / target_div;
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return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
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}
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static void dce60_pplib_apply_display_requirements(
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struct dc *dc,
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struct dc_state *context)
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{
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struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
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pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
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dce110_fill_display_configs(context, pp_display_cfg);
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if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)
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dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
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}
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static void dce60_update_clocks(struct clk_mgr *clk_mgr_base,
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struct dc_state *context,
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bool safe_to_lower)
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{
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struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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struct dm_pp_power_level_change_request level_change_req;
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int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
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/*TODO: W/A for dal3 linux, investigate why this works */
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if (!clk_mgr_dce->dfs_bypass_active)
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patched_disp_clk = patched_disp_clk * 115 / 100;
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level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
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/* get max clock state from PPLIB */
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if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
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|| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
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if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
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clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
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}
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if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
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patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk);
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clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
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}
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dce60_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
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}
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static struct clk_mgr_funcs dce60_funcs = {
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.get_dp_ref_clk_frequency = dce60_get_dp_ref_freq_khz,
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.update_clocks = dce60_update_clocks
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};
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void dce60_clk_mgr_construct(
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struct dc_context *ctx,
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struct clk_mgr_internal *clk_mgr)
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{
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dce_clk_mgr_construct(ctx, clk_mgr);
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memcpy(clk_mgr->max_clks_by_state,
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dce60_max_clks_by_state,
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sizeof(dce60_max_clks_by_state));
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clk_mgr->regs = &disp_clk_regs;
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clk_mgr->clk_mgr_shift = &disp_clk_shift;
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clk_mgr->clk_mgr_mask = &disp_clk_mask;
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clk_mgr->base.funcs = &dce60_funcs;
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}
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