/*
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* Copyright 2012-16 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "core_types.h"
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#include "clk_mgr_internal.h"
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#include "dce/dce_11_2_d.h"
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#include "dce/dce_11_2_sh_mask.h"
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#include "dce100/dce_clk_mgr.h"
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#include "dce110/dce110_clk_mgr.h"
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#include "dce112_clk_mgr.h"
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#include "dal_asic_id.h"
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/* set register offset */
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#define SR(reg_name)\
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.reg_name = mm ## reg_name
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/* set register offset with instance */
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#define SRI(reg_name, block, id)\
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.reg_name = mm ## block ## id ## _ ## reg_name
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static const struct clk_mgr_registers disp_clk_regs = {
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CLK_COMMON_REG_LIST_DCE_BASE()
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};
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static const struct clk_mgr_shift disp_clk_shift = {
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CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
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};
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static const struct clk_mgr_mask disp_clk_mask = {
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CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
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};
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static const struct state_dependent_clocks dce112_max_clks_by_state[] = {
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/*ClocksStateInvalid - should not be used*/
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{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
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/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
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{ .display_clk_khz = 389189, .pixel_clk_khz = 346672 },
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/*ClocksStateLow*/
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{ .display_clk_khz = 459000, .pixel_clk_khz = 400000 },
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/*ClocksStateNominal*/
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{ .display_clk_khz = 667000, .pixel_clk_khz = 600000 },
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/*ClocksStatePerformance*/
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{ .display_clk_khz = 1132000, .pixel_clk_khz = 600000 } };
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//TODO: remove use the two broken down functions
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int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz)
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{
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struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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struct bp_set_dce_clock_parameters dce_clk_params;
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struct dc_bios *bp = clk_mgr_base->ctx->dc_bios;
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struct dc *dc = clk_mgr_base->ctx->dc;
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struct dmcu *dmcu = dc->res_pool->dmcu;
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int actual_clock = requested_clk_khz;
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/* Prepare to program display clock*/
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memset(&dce_clk_params, 0, sizeof(dce_clk_params));
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/* Make sure requested clock isn't lower than minimum threshold*/
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requested_clk_khz = max(requested_clk_khz,
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clk_mgr_dce->base.dentist_vco_freq_khz / 62);
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dce_clk_params.target_clock_frequency = requested_clk_khz;
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dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
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dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK;
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bp->funcs->set_dce_clock(bp, &dce_clk_params);
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actual_clock = dce_clk_params.target_clock_frequency;
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/*
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* from power down, we need mark the clock state as ClocksStateNominal
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* from HWReset, so when resume we will call pplib voltage regulator.
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*/
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if (requested_clk_khz == 0)
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clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
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/*Program DP ref Clock*/
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/*VBIOS will determine DPREFCLK frequency, so we don't set it*/
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dce_clk_params.target_clock_frequency = 0;
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dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK;
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if (!ASICREV_IS_VEGA20_P(clk_mgr_base->ctx->asic_id.hw_internal_rev))
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dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =
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(dce_clk_params.pll_id ==
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CLOCK_SOURCE_COMBO_DISPLAY_PLL0);
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else
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dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false;
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bp->funcs->set_dce_clock(bp, &dce_clk_params);
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if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
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if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
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if (clk_mgr_dce->dfs_bypass_disp_clk != actual_clock)
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dmcu->funcs->set_psr_wait_loop(dmcu,
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actual_clock / 1000 / 7);
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}
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}
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clk_mgr_dce->dfs_bypass_disp_clk = actual_clock;
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return actual_clock;
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}
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int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz)
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{
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struct bp_set_dce_clock_parameters dce_clk_params;
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struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
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struct dc *dc = clk_mgr->base.ctx->dc;
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struct dmcu *dmcu = dc->res_pool->dmcu;
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int actual_clock = requested_clk_khz;
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/* Prepare to program display clock*/
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memset(&dce_clk_params, 0, sizeof(dce_clk_params));
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/* Make sure requested clock isn't lower than minimum threshold*/
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if (requested_clk_khz > 0)
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requested_clk_khz = max(requested_clk_khz,
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clk_mgr->base.dentist_vco_freq_khz / 62);
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dce_clk_params.target_clock_frequency = requested_clk_khz;
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dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
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dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK;
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bp->funcs->set_dce_clock(bp, &dce_clk_params);
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actual_clock = dce_clk_params.target_clock_frequency;
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/*
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* from power down, we need mark the clock state as ClocksStateNominal
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* from HWReset, so when resume we will call pplib voltage regulator.
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*/
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if (requested_clk_khz == 0)
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clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
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if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
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if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
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if (clk_mgr->dfs_bypass_disp_clk != actual_clock)
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dmcu->funcs->set_psr_wait_loop(dmcu,
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actual_clock / 1000 / 7);
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}
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}
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clk_mgr->dfs_bypass_disp_clk = actual_clock;
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return actual_clock;
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}
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int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr)
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{
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struct bp_set_dce_clock_parameters dce_clk_params;
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struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
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memset(&dce_clk_params, 0, sizeof(dce_clk_params));
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/*Program DP ref Clock*/
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/*VBIOS will determine DPREFCLK frequency, so we don't set it*/
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dce_clk_params.target_clock_frequency = 0;
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dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
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dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK;
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if (!ASICREV_IS_VEGA20_P(clk_mgr->base.ctx->asic_id.hw_internal_rev))
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dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =
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(dce_clk_params.pll_id ==
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CLOCK_SOURCE_COMBO_DISPLAY_PLL0);
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else
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dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false;
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bp->funcs->set_dce_clock(bp, &dce_clk_params);
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/* Returns the dp_refclk that was set */
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return dce_clk_params.target_clock_frequency;
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}
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static void dce112_update_clocks(struct clk_mgr *clk_mgr_base,
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struct dc_state *context,
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bool safe_to_lower)
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{
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struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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struct dm_pp_power_level_change_request level_change_req;
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int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
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/*TODO: W/A for dal3 linux, investigate why this works */
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if (!clk_mgr_dce->dfs_bypass_active)
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patched_disp_clk = patched_disp_clk * 115 / 100;
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level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
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/* get max clock state from PPLIB */
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if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
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|| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
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if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
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clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
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}
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if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
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patched_disp_clk = dce112_set_clock(clk_mgr_base, patched_disp_clk);
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clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
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}
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dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
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}
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static struct clk_mgr_funcs dce112_funcs = {
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.get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
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.update_clocks = dce112_update_clocks
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};
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void dce112_clk_mgr_construct(
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struct dc_context *ctx,
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struct clk_mgr_internal *clk_mgr)
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{
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dce_clk_mgr_construct(ctx, clk_mgr);
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memcpy(clk_mgr->max_clks_by_state,
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dce112_max_clks_by_state,
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sizeof(dce112_max_clks_by_state));
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clk_mgr->regs = &disp_clk_regs;
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clk_mgr->clk_mgr_shift = &disp_clk_shift;
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clk_mgr->clk_mgr_mask = &disp_clk_mask;
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clk_mgr->base.funcs = &dce112_funcs;
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}
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