/*
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* Copyright 2012-16 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dccg.h"
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#include "clk_mgr_internal.h"
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#include "dce_clk_mgr.h"
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#include "dce110/dce110_clk_mgr.h"
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#include "dce112/dce112_clk_mgr.h"
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#include "reg_helper.h"
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#include "dmcu.h"
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#include "core_types.h"
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#include "dal_asic_id.h"
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/*
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* Currently the register shifts and masks in this file are used for dce100 and dce80
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* which has identical definitions.
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* TODO: remove this when DPREFCLK_CNTL and dpref DENTIST_DISPCLK_CNTL
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* is moved to dccg, where it belongs
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*/
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#include "dce/dce_8_0_d.h"
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#include "dce/dce_8_0_sh_mask.h"
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#define REG(reg) \
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(clk_mgr->regs->reg)
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#undef FN
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#define FN(reg_name, field_name) \
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clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
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static const struct clk_mgr_registers disp_clk_regs = {
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CLK_COMMON_REG_LIST_DCE_BASE()
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};
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static const struct clk_mgr_shift disp_clk_shift = {
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CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
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};
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static const struct clk_mgr_mask disp_clk_mask = {
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CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
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};
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/* Max clock values for each state indexed by "enum clocks_state": */
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static const struct state_dependent_clocks dce80_max_clks_by_state[] = {
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/* ClocksStateInvalid - should not be used */
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{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
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/* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
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{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
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/* ClocksStateLow */
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{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
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/* ClocksStateNominal */
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{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
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/* ClocksStatePerformance */
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{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
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int dentist_get_divider_from_did(int did)
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{
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if (did < DENTIST_BASE_DID_1)
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did = DENTIST_BASE_DID_1;
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if (did > DENTIST_MAX_DID)
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did = DENTIST_MAX_DID;
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if (did < DENTIST_BASE_DID_2) {
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return DENTIST_DIVIDER_RANGE_1_START + DENTIST_DIVIDER_RANGE_1_STEP
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* (did - DENTIST_BASE_DID_1);
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} else if (did < DENTIST_BASE_DID_3) {
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return DENTIST_DIVIDER_RANGE_2_START + DENTIST_DIVIDER_RANGE_2_STEP
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* (did - DENTIST_BASE_DID_2);
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} else if (did < DENTIST_BASE_DID_4) {
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return DENTIST_DIVIDER_RANGE_3_START + DENTIST_DIVIDER_RANGE_3_STEP
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* (did - DENTIST_BASE_DID_3);
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} else {
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return DENTIST_DIVIDER_RANGE_4_START + DENTIST_DIVIDER_RANGE_4_STEP
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* (did - DENTIST_BASE_DID_4);
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}
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}
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/* SW will adjust DP REF Clock average value for all purposes
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* (DP DTO / DP Audio DTO and DP GTC)
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if clock is spread for all cases:
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-if SS enabled on DP Ref clock and HW de-spreading enabled with SW
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calculations for DS_INCR/DS_MODULO (this is planned to be default case)
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-if SS enabled on DP Ref clock and HW de-spreading enabled with HW
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calculations (not planned to be used, but average clock should still
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be valid)
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-if SS enabled on DP Ref clock and HW de-spreading disabled
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(should not be case with CIK) then SW should program all rates
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generated according to average value (case as with previous ASICs)
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*/
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int dce_adjust_dp_ref_freq_for_ss(struct clk_mgr_internal *clk_mgr_dce, int dp_ref_clk_khz)
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{
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if (clk_mgr_dce->ss_on_dprefclk && clk_mgr_dce->dprefclk_ss_divider != 0) {
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struct fixed31_32 ss_percentage = dc_fixpt_div_int(
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dc_fixpt_from_fraction(clk_mgr_dce->dprefclk_ss_percentage,
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clk_mgr_dce->dprefclk_ss_divider), 200);
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struct fixed31_32 adj_dp_ref_clk_khz;
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ss_percentage = dc_fixpt_sub(dc_fixpt_one, ss_percentage);
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adj_dp_ref_clk_khz = dc_fixpt_mul_int(ss_percentage, dp_ref_clk_khz);
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dp_ref_clk_khz = dc_fixpt_floor(adj_dp_ref_clk_khz);
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}
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return dp_ref_clk_khz;
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}
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int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
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{
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struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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int dprefclk_wdivider;
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int dprefclk_src_sel;
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int dp_ref_clk_khz;
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int target_div;
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/* ASSERT DP Reference Clock source is from DFS*/
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REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel);
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ASSERT(dprefclk_src_sel == 0);
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/* Read the mmDENTIST_DISPCLK_CNTL to get the currently
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* programmed DID DENTIST_DPREFCLK_WDIVIDER*/
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REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider);
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/* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/
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target_div = dentist_get_divider_from_did(dprefclk_wdivider);
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/* Calculate the current DFS clock, in kHz.*/
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dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
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* clk_mgr->base.dentist_vco_freq_khz) / target_div;
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return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
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}
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int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
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{
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struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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return dce_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_base->dprefclk_khz);
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}
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/* unit: in_khz before mode set, get pixel clock from context. ASIC register
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* may not be programmed yet
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*/
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uint32_t dce_get_max_pixel_clock_for_all_paths(struct dc_state *context)
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{
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uint32_t max_pix_clk = 0;
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int i;
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for (i = 0; i < MAX_PIPES; i++) {
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struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
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if (pipe_ctx->stream == NULL)
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continue;
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/* do not check under lay */
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if (pipe_ctx->top_pipe)
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continue;
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if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk)
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max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
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/* raise clock state for HBR3/2 if required. Confirmed with HW DCE/DPCS
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* logic for HBR3 still needs Nominal (0.8V) on VDDC rail
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*/
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if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
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pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk)
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max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk;
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}
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return max_pix_clk;
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}
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enum dm_pp_clocks_state dce_get_required_clocks_state(
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struct clk_mgr *clk_mgr_base,
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struct dc_state *context)
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{
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struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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int i;
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enum dm_pp_clocks_state low_req_clk;
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int max_pix_clk = dce_get_max_pixel_clock_for_all_paths(context);
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/* Iterate from highest supported to lowest valid state, and update
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* lowest RequiredState with the lowest state that satisfies
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* all required clocks
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*/
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for (i = clk_mgr_dce->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--)
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if (context->bw_ctx.bw.dce.dispclk_khz >
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clk_mgr_dce->max_clks_by_state[i].display_clk_khz
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|| max_pix_clk >
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clk_mgr_dce->max_clks_by_state[i].pixel_clk_khz)
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break;
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low_req_clk = i + 1;
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if (low_req_clk > clk_mgr_dce->max_clks_state) {
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/* set max clock state for high phyclock, invalid on exceeding display clock */
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if (clk_mgr_dce->max_clks_by_state[clk_mgr_dce->max_clks_state].display_clk_khz
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< context->bw_ctx.bw.dce.dispclk_khz)
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low_req_clk = DM_PP_CLOCKS_STATE_INVALID;
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else
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low_req_clk = clk_mgr_dce->max_clks_state;
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}
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return low_req_clk;
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}
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/* TODO: remove use the two broken down functions */
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int dce_set_clock(
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struct clk_mgr *clk_mgr_base,
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int requested_clk_khz)
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{
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struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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struct bp_pixel_clock_parameters pxl_clk_params = { 0 };
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struct dc_bios *bp = clk_mgr_base->ctx->dc_bios;
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int actual_clock = requested_clk_khz;
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struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu;
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/* Make sure requested clock isn't lower than minimum threshold*/
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if (requested_clk_khz > 0)
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requested_clk_khz = max(requested_clk_khz,
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clk_mgr_dce->base.dentist_vco_freq_khz / 64);
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/* Prepare to program display clock*/
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pxl_clk_params.target_pixel_clock_100hz = requested_clk_khz * 10;
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pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
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if (clk_mgr_dce->dfs_bypass_active)
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pxl_clk_params.flags.SET_DISPCLK_DFS_BYPASS = true;
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bp->funcs->program_display_engine_pll(bp, &pxl_clk_params);
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if (clk_mgr_dce->dfs_bypass_active) {
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/* Cache the fixed display clock*/
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clk_mgr_dce->dfs_bypass_disp_clk =
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pxl_clk_params.dfs_bypass_display_clock;
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actual_clock = pxl_clk_params.dfs_bypass_display_clock;
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}
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/* from power down, we need mark the clock state as ClocksStateNominal
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* from HWReset, so when resume we will call pplib voltage regulator.*/
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if (requested_clk_khz == 0)
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clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
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if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
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dmcu->funcs->set_psr_wait_loop(dmcu, actual_clock / 1000 / 7);
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return actual_clock;
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}
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static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce)
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{
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struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug;
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struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
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int i;
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if (bp->integrated_info)
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clk_mgr_dce->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
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if (clk_mgr_dce->base.dentist_vco_freq_khz == 0) {
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clk_mgr_dce->base.dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
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if (clk_mgr_dce->base.dentist_vco_freq_khz == 0)
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clk_mgr_dce->base.dentist_vco_freq_khz = 3600000;
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}
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/*update the maximum display clock for each power state*/
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for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
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enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID;
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switch (i) {
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case 0:
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clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW;
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break;
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case 1:
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clk_state = DM_PP_CLOCKS_STATE_LOW;
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break;
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case 2:
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clk_state = DM_PP_CLOCKS_STATE_NOMINAL;
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break;
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case 3:
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clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE;
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break;
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default:
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clk_state = DM_PP_CLOCKS_STATE_INVALID;
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break;
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}
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/*Do not allow bad VBIOS/SBIOS to override with invalid values,
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* check for > 100MHz*/
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if (bp->integrated_info)
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if (bp->integrated_info->disp_clk_voltage[i].max_supported_clk >= 100000)
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clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz =
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bp->integrated_info->disp_clk_voltage[i].max_supported_clk;
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}
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if (!debug->disable_dfs_bypass && bp->integrated_info)
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if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
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clk_mgr_dce->dfs_bypass_enabled = true;
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}
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void dce_clock_read_ss_info(struct clk_mgr_internal *clk_mgr_dce)
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{
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struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
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int ss_info_num = bp->funcs->get_ss_entry_number(
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bp, AS_SIGNAL_TYPE_GPU_PLL);
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if (ss_info_num) {
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struct spread_spectrum_info info = { { 0 } };
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enum bp_result result = bp->funcs->get_spread_spectrum_info(
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bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);
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/* Based on VBIOS, VBIOS will keep entry for GPU PLL SS
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* even if SS not enabled and in that case
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* SSInfo.spreadSpectrumPercentage !=0 would be sign
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* that SS is enabled
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*/
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if (result == BP_RESULT_OK &&
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info.spread_spectrum_percentage != 0) {
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clk_mgr_dce->ss_on_dprefclk = true;
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clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider;
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if (info.type.CENTER_MODE == 0) {
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/* TODO: Currently for DP Reference clock we
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* need only SS percentage for
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* downspread */
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clk_mgr_dce->dprefclk_ss_percentage =
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info.spread_spectrum_percentage;
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}
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return;
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}
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result = bp->funcs->get_spread_spectrum_info(
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bp, AS_SIGNAL_TYPE_DISPLAY_PORT, 0, &info);
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/* Based on VBIOS, VBIOS will keep entry for DPREFCLK SS
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* even if SS not enabled and in that case
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* SSInfo.spreadSpectrumPercentage !=0 would be sign
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* that SS is enabled
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*/
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if (result == BP_RESULT_OK &&
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info.spread_spectrum_percentage != 0) {
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clk_mgr_dce->ss_on_dprefclk = true;
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clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider;
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if (info.type.CENTER_MODE == 0) {
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/* Currently for DP Reference clock we
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* need only SS percentage for
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* downspread */
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clk_mgr_dce->dprefclk_ss_percentage =
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info.spread_spectrum_percentage;
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}
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}
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}
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}
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static void dce_pplib_apply_display_requirements(
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struct dc *dc,
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struct dc_state *context)
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{
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struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
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pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
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dce110_fill_display_configs(context, pp_display_cfg);
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if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)
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dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
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}
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static void dce_update_clocks(struct clk_mgr *clk_mgr_base,
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struct dc_state *context,
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bool safe_to_lower)
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{
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struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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struct dm_pp_power_level_change_request level_change_req;
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int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
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/*TODO: W/A for dal3 linux, investigate why this works */
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if (!clk_mgr_dce->dfs_bypass_active)
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patched_disp_clk = patched_disp_clk * 115 / 100;
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level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
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/* get max clock state from PPLIB */
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if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
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|| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
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if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
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clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
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}
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if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
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patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk);
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clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
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}
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dce_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
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}
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static struct clk_mgr_funcs dce_funcs = {
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.get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
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.update_clocks = dce_update_clocks
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};
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void dce_clk_mgr_construct(
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struct dc_context *ctx,
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struct clk_mgr_internal *clk_mgr)
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{
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struct clk_mgr *base = &clk_mgr->base;
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struct dm_pp_static_clock_info static_clk_info = {0};
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memcpy(clk_mgr->max_clks_by_state,
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dce80_max_clks_by_state,
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sizeof(dce80_max_clks_by_state));
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base->ctx = ctx;
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base->funcs = &dce_funcs;
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clk_mgr->regs = &disp_clk_regs;
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clk_mgr->clk_mgr_shift = &disp_clk_shift;
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clk_mgr->clk_mgr_mask = &disp_clk_mask;
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clk_mgr->dfs_bypass_disp_clk = 0;
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clk_mgr->dprefclk_ss_percentage = 0;
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clk_mgr->dprefclk_ss_divider = 1000;
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clk_mgr->ss_on_dprefclk = false;
|
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if (dm_pp_get_static_clocks(ctx, &static_clk_info))
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clk_mgr->max_clks_state = static_clk_info.max_clocks_state;
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else
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clk_mgr->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
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clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
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dce_clock_read_integrated_info(clk_mgr);
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dce_clock_read_ss_info(clk_mgr);
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}
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