/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "kfd_device_queue_manager.h"
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#include "gca/gfx_8_0_enum.h"
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#include "gca/gfx_8_0_sh_mask.h"
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#include "oss/oss_3_0_sh_mask.h"
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static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd,
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enum cache_policy default_policy,
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enum cache_policy alternate_policy,
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void __user *alternate_aperture_base,
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uint64_t alternate_aperture_size);
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static bool set_cache_memory_policy_vi_tonga(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd,
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enum cache_policy default_policy,
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enum cache_policy alternate_policy,
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void __user *alternate_aperture_base,
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uint64_t alternate_aperture_size);
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static int update_qpd_vi(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd);
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static int update_qpd_vi_tonga(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd);
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static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
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struct qcm_process_device *qpd);
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static void init_sdma_vm_tonga(struct device_queue_manager *dqm,
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struct queue *q,
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struct qcm_process_device *qpd);
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void device_queue_manager_init_vi(
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struct device_queue_manager_asic_ops *asic_ops)
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{
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asic_ops->set_cache_memory_policy = set_cache_memory_policy_vi;
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asic_ops->update_qpd = update_qpd_vi;
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asic_ops->init_sdma_vm = init_sdma_vm;
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asic_ops->mqd_manager_init = mqd_manager_init_vi;
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}
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void device_queue_manager_init_vi_tonga(
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struct device_queue_manager_asic_ops *asic_ops)
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{
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asic_ops->set_cache_memory_policy = set_cache_memory_policy_vi_tonga;
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asic_ops->update_qpd = update_qpd_vi_tonga;
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asic_ops->init_sdma_vm = init_sdma_vm_tonga;
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asic_ops->mqd_manager_init = mqd_manager_init_vi_tonga;
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}
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static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble)
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{
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/* In 64-bit mode, we can only control the top 3 bits of the LDS,
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* scratch and GPUVM apertures.
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* The hardware fills in the remaining 59 bits according to the
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* following pattern:
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* LDS: X0000000'00000000 - X0000001'00000000 (4GB)
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* Scratch: X0000001'00000000 - X0000002'00000000 (4GB)
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* GPUVM: Y0010000'00000000 - Y0020000'00000000 (1TB)
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*
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* (where X/Y is the configurable nybble with the low-bit 0)
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*
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* LDS and scratch will have the same top nybble programmed in the
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* top 3 bits of SH_MEM_BASES.PRIVATE_BASE.
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* GPUVM can have a different top nybble programmed in the
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* top 3 bits of SH_MEM_BASES.SHARED_BASE.
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* We don't bother to support different top nybbles
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* for LDS/Scratch and GPUVM.
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*/
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WARN_ON((top_address_nybble & 1) || top_address_nybble > 0xE ||
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top_address_nybble == 0);
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return top_address_nybble << 12 |
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(top_address_nybble << 12) <<
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SH_MEM_BASES__SHARED_BASE__SHIFT;
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}
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static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd,
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enum cache_policy default_policy,
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enum cache_policy alternate_policy,
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void __user *alternate_aperture_base,
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uint64_t alternate_aperture_size)
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{
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uint32_t default_mtype;
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uint32_t ape1_mtype;
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default_mtype = (default_policy == cache_policy_coherent) ?
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MTYPE_CC :
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MTYPE_NC;
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ape1_mtype = (alternate_policy == cache_policy_coherent) ?
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MTYPE_CC :
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MTYPE_NC;
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qpd->sh_mem_config = (qpd->sh_mem_config &
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SH_MEM_CONFIG__ADDRESS_MODE_MASK) |
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SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
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SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
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default_mtype << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
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ape1_mtype << SH_MEM_CONFIG__APE1_MTYPE__SHIFT |
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SH_MEM_CONFIG__PRIVATE_ATC_MASK;
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return true;
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}
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static bool set_cache_memory_policy_vi_tonga(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd,
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enum cache_policy default_policy,
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enum cache_policy alternate_policy,
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void __user *alternate_aperture_base,
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uint64_t alternate_aperture_size)
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{
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uint32_t default_mtype;
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uint32_t ape1_mtype;
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default_mtype = (default_policy == cache_policy_coherent) ?
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MTYPE_UC :
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MTYPE_NC;
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ape1_mtype = (alternate_policy == cache_policy_coherent) ?
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MTYPE_UC :
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MTYPE_NC;
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qpd->sh_mem_config =
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SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
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SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
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default_mtype << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
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ape1_mtype << SH_MEM_CONFIG__APE1_MTYPE__SHIFT;
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return true;
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}
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static int update_qpd_vi(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd)
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{
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struct kfd_process_device *pdd;
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unsigned int temp;
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pdd = qpd_to_pdd(qpd);
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/* check if sh_mem_config register already configured */
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if (qpd->sh_mem_config == 0) {
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qpd->sh_mem_config =
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SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
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SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
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MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
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MTYPE_CC << SH_MEM_CONFIG__APE1_MTYPE__SHIFT |
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SH_MEM_CONFIG__PRIVATE_ATC_MASK;
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qpd->sh_mem_ape1_limit = 0;
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qpd->sh_mem_ape1_base = 0;
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}
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if (qpd->pqm->process->is_32bit_user_mode) {
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temp = get_sh_mem_bases_32(pdd);
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qpd->sh_mem_bases = temp << SH_MEM_BASES__SHARED_BASE__SHIFT;
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qpd->sh_mem_config |= SH_MEM_ADDRESS_MODE_HSA32 <<
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SH_MEM_CONFIG__ADDRESS_MODE__SHIFT;
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} else {
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temp = get_sh_mem_bases_nybble_64(pdd);
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qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp);
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qpd->sh_mem_config |= SH_MEM_ADDRESS_MODE_HSA64 <<
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SH_MEM_CONFIG__ADDRESS_MODE__SHIFT;
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qpd->sh_mem_config |= 1 <<
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SH_MEM_CONFIG__PRIVATE_ATC__SHIFT;
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}
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pr_debug("is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n",
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qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases);
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return 0;
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}
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static int update_qpd_vi_tonga(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd)
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{
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struct kfd_process_device *pdd;
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unsigned int temp;
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pdd = qpd_to_pdd(qpd);
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/* check if sh_mem_config register already configured */
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if (qpd->sh_mem_config == 0) {
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qpd->sh_mem_config =
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SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
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SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
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MTYPE_UC <<
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SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
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MTYPE_UC <<
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SH_MEM_CONFIG__APE1_MTYPE__SHIFT;
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qpd->sh_mem_ape1_limit = 0;
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qpd->sh_mem_ape1_base = 0;
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}
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/* On dGPU we're always in GPUVM64 addressing mode with 64-bit
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* aperture addresses.
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*/
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temp = get_sh_mem_bases_nybble_64(pdd);
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qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp);
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pr_debug("sh_mem_bases nybble: 0x%X and register 0x%X\n",
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temp, qpd->sh_mem_bases);
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return 0;
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}
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static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
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struct qcm_process_device *qpd)
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{
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uint32_t value = (1 << SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT);
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if (q->process->is_32bit_user_mode)
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value |= (1 << SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT) |
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get_sh_mem_bases_32(qpd_to_pdd(qpd));
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else
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value |= ((get_sh_mem_bases_nybble_64(qpd_to_pdd(qpd))) <<
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SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT) &
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SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK;
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q->properties.sdma_vm_addr = value;
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}
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static void init_sdma_vm_tonga(struct device_queue_manager *dqm,
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struct queue *q,
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struct qcm_process_device *qpd)
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{
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/* On dGPU we're always in GPUVM64 addressing mode with 64-bit
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* aperture addresses.
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*/
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q->properties.sdma_vm_addr =
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((get_sh_mem_bases_nybble_64(qpd_to_pdd(qpd))) <<
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SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT) &
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SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK;
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}
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