/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "kfd_device_queue_manager.h"
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#include "navi10_enum.h"
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#include "gc/gc_10_1_0_offset.h"
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#include "gc/gc_10_1_0_sh_mask.h"
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static int update_qpd_v10(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd);
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static void init_sdma_vm_v10(struct device_queue_manager *dqm, struct queue *q,
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struct qcm_process_device *qpd);
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void device_queue_manager_init_v10_navi10(
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struct device_queue_manager_asic_ops *asic_ops)
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{
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asic_ops->update_qpd = update_qpd_v10;
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asic_ops->init_sdma_vm = init_sdma_vm_v10;
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asic_ops->mqd_manager_init = mqd_manager_init_v10;
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}
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static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)
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{
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uint32_t shared_base = pdd->lds_base >> 48;
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uint32_t private_base = pdd->scratch_base >> 48;
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return (shared_base << SH_MEM_BASES__SHARED_BASE__SHIFT) |
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private_base;
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}
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static int update_qpd_v10(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd)
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{
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struct kfd_process_device *pdd;
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pdd = qpd_to_pdd(qpd);
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/* check if sh_mem_config register already configured */
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if (qpd->sh_mem_config == 0) {
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qpd->sh_mem_config =
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(SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
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SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |
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(3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);
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#if 0
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/* TODO:
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* This shouldn't be an issue with Navi10. Verify.
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*/
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if (vega10_noretry)
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qpd->sh_mem_config |=
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1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;
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#endif
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qpd->sh_mem_ape1_limit = 0;
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qpd->sh_mem_ape1_base = 0;
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}
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qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd);
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pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases);
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return 0;
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}
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static void init_sdma_vm_v10(struct device_queue_manager *dqm, struct queue *q,
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struct qcm_process_device *qpd)
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{
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/* Not needed on SDMAv4 onwards any more */
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q->properties.sdma_vm_addr = 0;
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}
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