/* SPDX-License-Identifier: GPL-2.0
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* Marvell OcteonTX CPT driver
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*
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* Copyright (C) 2019 Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __OTX_CPTVF_H
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#define __OTX_CPTVF_H
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#include <linux/list.h>
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#include <linux/interrupt.h>
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#include <linux/device.h>
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#include "otx_cpt_common.h"
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#include "otx_cptvf_reqmgr.h"
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/* Flags to indicate the features supported */
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#define OTX_CPT_FLAG_DEVICE_READY BIT(1)
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#define otx_cpt_device_ready(cpt) ((cpt)->flags & OTX_CPT_FLAG_DEVICE_READY)
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/* Default command queue length */
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#define OTX_CPT_CMD_QLEN (4*2046)
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#define OTX_CPT_CMD_QCHUNK_SIZE 1023
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#define OTX_CPT_NUM_QS_PER_VF 1
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struct otx_cpt_cmd_chunk {
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u8 *head;
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dma_addr_t dma_addr;
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u32 size; /* Chunk size, max OTX_CPT_INST_CHUNK_MAX_SIZE */
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struct list_head nextchunk;
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};
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struct otx_cpt_cmd_queue {
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u32 idx; /* Command queue host write idx */
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u32 num_chunks; /* Number of command chunks */
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struct otx_cpt_cmd_chunk *qhead;/*
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* Command queue head, instructions
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* are inserted here
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*/
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struct otx_cpt_cmd_chunk *base;
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struct list_head chead;
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};
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struct otx_cpt_cmd_qinfo {
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u32 qchunksize; /* Command queue chunk size */
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struct otx_cpt_cmd_queue queue[OTX_CPT_NUM_QS_PER_VF];
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};
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struct otx_cpt_pending_qinfo {
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u32 num_queues; /* Number of queues supported */
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struct otx_cpt_pending_queue queue[OTX_CPT_NUM_QS_PER_VF];
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};
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#define for_each_pending_queue(qinfo, q, i) \
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for (i = 0, q = &qinfo->queue[i]; i < qinfo->num_queues; i++, \
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q = &qinfo->queue[i])
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struct otx_cptvf_wqe {
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struct tasklet_struct twork;
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struct otx_cptvf *cptvf;
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};
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struct otx_cptvf_wqe_info {
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struct otx_cptvf_wqe vq_wqe[OTX_CPT_NUM_QS_PER_VF];
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};
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struct otx_cptvf {
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u16 flags; /* Flags to hold device status bits */
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u8 vfid; /* Device Index 0...OTX_CPT_MAX_VF_NUM */
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u8 num_vfs; /* Number of enabled VFs */
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u8 vftype; /* VF type of SE_TYPE(2) or AE_TYPE(1) */
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u8 vfgrp; /* VF group (0 - 8) */
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u8 node; /* Operating node: Bits (46:44) in BAR0 address */
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u8 priority; /*
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* VF priority ring: 1-High proirity round
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* robin ring;0-Low priority round robin ring;
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*/
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struct pci_dev *pdev; /* Pci device handle */
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void __iomem *reg_base; /* Register start address */
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void *wqe_info; /* BH worker info */
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/* MSI-X */
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cpumask_var_t affinity_mask[OTX_CPT_VF_MSIX_VECTORS];
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/* Command and Pending queues */
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u32 qsize;
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u32 num_queues;
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struct otx_cpt_cmd_qinfo cqinfo; /* Command queue information */
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struct otx_cpt_pending_qinfo pqinfo; /* Pending queue information */
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/* VF-PF mailbox communication */
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bool pf_acked;
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bool pf_nacked;
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};
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int otx_cptvf_send_vf_up(struct otx_cptvf *cptvf);
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int otx_cptvf_send_vf_down(struct otx_cptvf *cptvf);
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int otx_cptvf_send_vf_to_grp_msg(struct otx_cptvf *cptvf, int group);
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int otx_cptvf_send_vf_priority_msg(struct otx_cptvf *cptvf);
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int otx_cptvf_send_vq_size_msg(struct otx_cptvf *cptvf);
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int otx_cptvf_check_pf_ready(struct otx_cptvf *cptvf);
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void otx_cptvf_handle_mbox_intr(struct otx_cptvf *cptvf);
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void otx_cptvf_write_vq_doorbell(struct otx_cptvf *cptvf, u32 val);
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#endif /* __OTX_CPTVF_H */
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