/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
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#ifndef __CC_FIPS_H__
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#define __CC_FIPS_H__
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#ifdef CONFIG_CRYPTO_FIPS
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enum cc_fips_status {
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CC_FIPS_SYNC_MODULE_OK = 0x0,
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CC_FIPS_SYNC_MODULE_ERROR = 0x1,
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CC_FIPS_SYNC_REE_STATUS = 0x4,
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CC_FIPS_SYNC_TEE_STATUS = 0x8,
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CC_FIPS_SYNC_STATUS_RESERVE32B = S32_MAX
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};
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int cc_fips_init(struct cc_drvdata *p_drvdata);
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void cc_fips_fini(struct cc_drvdata *drvdata);
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void fips_handler(struct cc_drvdata *drvdata);
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void cc_set_ree_fips_status(struct cc_drvdata *drvdata, bool ok);
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void cc_tee_handle_fips_error(struct cc_drvdata *p_drvdata);
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#else /* CONFIG_CRYPTO_FIPS */
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static inline int cc_fips_init(struct cc_drvdata *p_drvdata)
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{
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return 0;
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}
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static inline void cc_fips_fini(struct cc_drvdata *drvdata) {}
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static inline void cc_set_ree_fips_status(struct cc_drvdata *drvdata,
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bool ok) {}
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static inline void fips_handler(struct cc_drvdata *drvdata) {}
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static inline void cc_tee_handle_fips_error(struct cc_drvdata *p_drvdata) {}
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#endif /* CONFIG_CRYPTO_FIPS */
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#endif /*__CC_FIPS_H__*/
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