// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2012-2013 Xilinx
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*
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* CPU idle support for Xilinx Zynq
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*
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* based on arch/arm/mach-at91/cpuidle.c
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*
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* The cpu idle uses wait-for-interrupt and RAM self refresh in order
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* to implement two idle states -
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* #1 wait-for-interrupt
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* #2 wait-for-interrupt and RAM self refresh
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*
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* Maintainer: Michal Simek <michal.simek@xilinx.com>
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*/
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#include <linux/init.h>
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#include <linux/cpuidle.h>
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#include <linux/platform_device.h>
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#include <asm/cpuidle.h>
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#define ZYNQ_MAX_STATES 2
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/* Actual code that puts the SoC in different idle states */
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static int zynq_enter_idle(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index)
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{
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/* Add code for DDR self refresh start */
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cpu_do_idle();
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return index;
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}
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static struct cpuidle_driver zynq_idle_driver = {
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.name = "zynq_idle",
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.owner = THIS_MODULE,
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.states = {
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ARM_CPUIDLE_WFI_STATE,
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{
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.enter = zynq_enter_idle,
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.exit_latency = 10,
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.target_residency = 10000,
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.name = "RAM_SR",
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.desc = "WFI and RAM Self Refresh",
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},
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},
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.safe_state_index = 0,
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.state_count = ZYNQ_MAX_STATES,
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};
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/* Initialize CPU idle by registering the idle states */
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static int zynq_cpuidle_probe(struct platform_device *pdev)
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{
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pr_info("Xilinx Zynq CpuIdle Driver started\n");
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return cpuidle_register(&zynq_idle_driver, NULL);
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}
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static struct platform_driver zynq_cpuidle_driver = {
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.driver = {
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.name = "cpuidle-zynq",
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},
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.probe = zynq_cpuidle_probe,
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};
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builtin_platform_driver(zynq_cpuidle_driver);
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