1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
| /* SPDX-License-Identifier: GPL-2.0-only */
| /*
| * Clocks for ux500 platforms
| *
| * Copyright (C) 2012 ST-Ericsson SA
| * Author: Ulf Hansson <ulf.hansson@linaro.org>
| */
|
| #ifndef __UX500_CLK_H
| #define __UX500_CLK_H
|
| #include <linux/device.h>
| #include <linux/types.h>
|
| struct clk;
|
| struct clk *clk_reg_prcc_pclk(const char *name,
| const char *parent_name,
| resource_size_t phy_base,
| u32 cg_sel,
| unsigned long flags);
|
| struct clk *clk_reg_prcc_kclk(const char *name,
| const char *parent_name,
| resource_size_t phy_base,
| u32 cg_sel,
| unsigned long flags);
|
| struct clk *clk_reg_prcmu_scalable(const char *name,
| const char *parent_name,
| u8 cg_sel,
| unsigned long rate,
| unsigned long flags);
|
| struct clk *clk_reg_prcmu_gate(const char *name,
| const char *parent_name,
| u8 cg_sel,
| unsigned long flags);
|
| struct clk *clk_reg_prcmu_scalable_rate(const char *name,
| const char *parent_name,
| u8 cg_sel,
| unsigned long rate,
| unsigned long flags);
|
| struct clk *clk_reg_prcmu_rate(const char *name,
| const char *parent_name,
| u8 cg_sel,
| unsigned long flags);
|
| struct clk *clk_reg_prcmu_opp_gate(const char *name,
| const char *parent_name,
| u8 cg_sel,
| unsigned long flags);
|
| struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name,
| const char *parent_name,
| u8 cg_sel,
| unsigned long rate,
| unsigned long flags);
|
| struct clk *clk_reg_sysctrl_gate(struct device *dev,
| const char *name,
| const char *parent_name,
| u16 reg_sel,
| u8 reg_mask,
| u8 reg_bits,
| unsigned long enable_delay_us,
| unsigned long flags);
|
| struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev,
| const char *name,
| const char *parent_name,
| u16 reg_sel,
| u8 reg_mask,
| u8 reg_bits,
| unsigned long rate,
| unsigned long enable_delay_us,
| unsigned long flags);
|
| struct clk *clk_reg_sysctrl_set_parent(struct device *dev,
| const char *name,
| const char **parent_names,
| u8 num_parents,
| u16 *reg_sel,
| u8 *reg_mask,
| u8 *reg_bits,
| unsigned long flags);
|
| #endif /* __UX500_CLK_H */
|
|
