// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2014 Free Electrons
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*
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* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
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*
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* Allwinner A31 APB0 clock driver
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*/
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#include <linux/clk-provider.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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/*
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* The APB0 clk has a configurable divisor.
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*
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* We must use a clk_div_table and not a regular power of 2
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* divisor here, because the first 2 values divide the clock
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* by 2.
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*/
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static const struct clk_div_table sun6i_a31_apb0_divs[] = {
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{ .val = 0, .div = 2, },
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{ .val = 1, .div = 2, },
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{ .val = 2, .div = 4, },
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{ .val = 3, .div = 8, },
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{ /* sentinel */ },
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};
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static int sun6i_a31_apb0_clk_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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const char *clk_name = np->name;
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const char *clk_parent;
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struct resource *r;
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void __iomem *reg;
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struct clk *clk;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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reg = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(reg))
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return PTR_ERR(reg);
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clk_parent = of_clk_get_parent_name(np, 0);
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if (!clk_parent)
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return -EINVAL;
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of_property_read_string(np, "clock-output-names", &clk_name);
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clk = clk_register_divider_table(&pdev->dev, clk_name, clk_parent,
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0, reg, 0, 2, 0, sun6i_a31_apb0_divs,
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NULL);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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return of_clk_add_provider(np, of_clk_src_simple_get, clk);
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}
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static const struct of_device_id sun6i_a31_apb0_clk_dt_ids[] = {
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{ .compatible = "allwinner,sun6i-a31-apb0-clk" },
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{ /* sentinel */ }
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};
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static struct platform_driver sun6i_a31_apb0_clk_driver = {
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.driver = {
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.name = "sun6i-a31-apb0-clk",
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.of_match_table = sun6i_a31_apb0_clk_dt_ids,
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},
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.probe = sun6i_a31_apb0_clk_probe,
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};
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builtin_platform_driver(sun6i_a31_apb0_clk_driver);
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