/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2014, The Linux Foundation. All rights reserved. */
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#ifndef __QCOM_CLK_COMMON_H__
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#define __QCOM_CLK_COMMON_H__
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struct platform_device;
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struct regmap_config;
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struct clk_regmap;
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struct qcom_reset_map;
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struct regmap;
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struct freq_tbl;
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struct clk_hw;
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#define PLL_LOCK_COUNT_SHIFT 8
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#define PLL_LOCK_COUNT_MASK 0x3f
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#define PLL_BIAS_COUNT_SHIFT 14
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#define PLL_BIAS_COUNT_MASK 0x3f
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#define PLL_VOTE_FSM_ENA BIT(20)
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#define PLL_VOTE_FSM_RESET BIT(21)
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struct qcom_cc_desc {
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const struct regmap_config *config;
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struct clk_regmap **clks;
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size_t num_clks;
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const struct qcom_reset_map *resets;
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size_t num_resets;
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struct gdsc **gdscs;
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size_t num_gdscs;
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struct clk_hw **clk_hws;
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size_t num_clk_hws;
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};
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/**
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* struct parent_map - map table for source select configuration values
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* @src: source
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* @cfg: configuration value
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*/
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struct parent_map {
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u8 src;
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u8 cfg;
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};
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extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f,
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unsigned long rate);
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extern const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,
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unsigned long rate);
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extern void
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qcom_pll_set_fsm_mode(struct regmap *m, u32 reg, u8 bias_count, u8 lock_count);
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extern int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map,
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u8 src);
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extern int qcom_find_cfg_index(struct clk_hw *hw, const struct parent_map *map,
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u8 cfg);
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extern int qcom_cc_register_board_clk(struct device *dev, const char *path,
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const char *name, unsigned long rate);
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extern int qcom_cc_register_sleep_clk(struct device *dev);
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extern struct regmap *qcom_cc_map(struct platform_device *pdev,
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const struct qcom_cc_desc *desc);
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extern int qcom_cc_really_probe(struct platform_device *pdev,
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const struct qcom_cc_desc *desc,
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struct regmap *regmap);
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extern int qcom_cc_probe(struct platform_device *pdev,
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const struct qcom_cc_desc *desc);
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extern int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
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const struct qcom_cc_desc *desc);
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#endif
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