/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, Linaro Limited
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* Author: Georgi Djakov <georgi.djakov@linaro.org>
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*/
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#ifndef __QCOM_CLK_REGMAP_MUX_DIV_H__
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#define __QCOM_CLK_REGMAP_MUX_DIV_H__
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#include <linux/clk-provider.h>
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#include "clk-regmap.h"
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/**
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* struct mux_div_clk - combined mux/divider clock
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* @reg_offset: offset of the mux/divider register
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* @hid_width: number of bits in half integer divider
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* @hid_shift: lowest bit of hid value field
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* @src_width: number of bits in source select
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* @src_shift: lowest bit of source select field
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* @div: the divider raw configuration value
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* @src: the mux index which will be used if the clock is enabled
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* @parent_map: map from parent_names index to src_sel field
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* @clkr: handle between common and hardware-specific interfaces
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* @pclk: the input PLL clock
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* @clk_nb: clock notifier for rate changes of the input PLL
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*/
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struct clk_regmap_mux_div {
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u32 reg_offset;
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u32 hid_width;
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u32 hid_shift;
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u32 src_width;
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u32 src_shift;
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u32 div;
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u32 src;
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const u32 *parent_map;
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struct clk_regmap clkr;
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struct clk *pclk;
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struct notifier_block clk_nb;
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};
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extern const struct clk_ops clk_regmap_mux_div_ops;
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extern int mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div);
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#endif
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