// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (c) 2018 MediaTek Inc.
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// Author: Weiyi Lu <weiyi.lu@mediatek.com>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt8183-clk.h>
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static const struct mtk_gate_regs vdec0_cg_regs = {
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.set_ofs = 0x0,
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.clr_ofs = 0x4,
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.sta_ofs = 0x0,
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};
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static const struct mtk_gate_regs vdec1_cg_regs = {
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.set_ofs = 0x8,
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.clr_ofs = 0xc,
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.sta_ofs = 0x8,
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};
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#define GATE_VDEC0_I(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \
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&mtk_clk_gate_ops_setclr_inv)
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#define GATE_VDEC1_I(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \
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&mtk_clk_gate_ops_setclr_inv)
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static const struct mtk_gate vdec_clks[] = {
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/* VDEC0 */
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GATE_VDEC0_I(CLK_VDEC_VDEC, "vdec_vdec", "mm_sel", 0),
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/* VDEC1 */
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GATE_VDEC1_I(CLK_VDEC_LARB1, "vdec_larb1", "mm_sel", 0),
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};
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static int clk_mt8183_vdec_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
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mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
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clk_data);
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return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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}
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static const struct of_device_id of_match_clk_mt8183_vdec[] = {
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{ .compatible = "mediatek,mt8183-vdecsys", },
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{}
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};
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static struct platform_driver clk_mt8183_vdec_drv = {
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.probe = clk_mt8183_vdec_probe,
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.driver = {
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.name = "clk-mt8183-vdec",
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.of_match_table = of_match_clk_mt8183_vdec,
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},
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};
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builtin_platform_driver(clk_mt8183_vdec_drv);
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