// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2014 Lucas Stach <l.stach@pengutronix.de>, Pengutronix
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/export.h>
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#include <linux/slab.h>
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#include "clk.h"
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struct clk_cpu {
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struct clk_hw hw;
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struct clk *div;
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struct clk *mux;
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struct clk *pll;
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struct clk *step;
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};
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static inline struct clk_cpu *to_clk_cpu(struct clk_hw *hw)
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{
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return container_of(hw, struct clk_cpu, hw);
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}
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static unsigned long clk_cpu_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_cpu *cpu = to_clk_cpu(hw);
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return clk_get_rate(cpu->div);
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}
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static long clk_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_cpu *cpu = to_clk_cpu(hw);
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return clk_round_rate(cpu->pll, rate);
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}
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static int clk_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_cpu *cpu = to_clk_cpu(hw);
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int ret;
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/* switch to PLL bypass clock */
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ret = clk_set_parent(cpu->mux, cpu->step);
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if (ret)
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return ret;
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/* reprogram PLL */
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ret = clk_set_rate(cpu->pll, rate);
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if (ret) {
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clk_set_parent(cpu->mux, cpu->pll);
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return ret;
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}
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/* switch back to PLL clock */
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clk_set_parent(cpu->mux, cpu->pll);
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/* Ensure the divider is what we expect */
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clk_set_rate(cpu->div, rate);
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return 0;
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}
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static const struct clk_ops clk_cpu_ops = {
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.recalc_rate = clk_cpu_recalc_rate,
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.round_rate = clk_cpu_round_rate,
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.set_rate = clk_cpu_set_rate,
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};
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struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
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struct clk *div, struct clk *mux, struct clk *pll,
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struct clk *step)
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{
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struct clk_cpu *cpu;
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struct clk_hw *hw;
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struct clk_init_data init;
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int ret;
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cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
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if (!cpu)
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return ERR_PTR(-ENOMEM);
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cpu->div = div;
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cpu->mux = mux;
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cpu->pll = pll;
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cpu->step = step;
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init.name = name;
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init.ops = &clk_cpu_ops;
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init.flags = CLK_IS_CRITICAL;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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cpu->hw.init = &init;
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hw = &cpu->hw;
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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kfree(cpu);
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return ERR_PTR(ret);
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}
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return hw;
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}
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EXPORT_SYMBOL_GPL(imx_clk_hw_cpu);
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