// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* clk-h32mx.c
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*
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* Copyright (C) 2014 Atmel
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*
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* Alexandre Belloni <alexandre.belloni@free-electrons.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/at91_pmc.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include "pmc.h"
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#define H32MX_MAX_FREQ 90000000
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struct clk_sama5d4_h32mx {
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struct clk_hw hw;
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struct regmap *regmap;
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};
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#define to_clk_sama5d4_h32mx(hw) container_of(hw, struct clk_sama5d4_h32mx, hw)
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static unsigned long clk_sama5d4_h32mx_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw);
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unsigned int mckr;
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regmap_read(h32mxclk->regmap, AT91_PMC_MCKR, &mckr);
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if (mckr & AT91_PMC_H32MXDIV)
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return parent_rate / 2;
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if (parent_rate > H32MX_MAX_FREQ)
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pr_warn("H32MX clock is too fast\n");
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return parent_rate;
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}
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static long clk_sama5d4_h32mx_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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unsigned long div;
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if (rate > *parent_rate)
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return *parent_rate;
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div = *parent_rate / 2;
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if (rate < div)
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return div;
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if (rate - div < *parent_rate - rate)
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return div;
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return *parent_rate;
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}
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static int clk_sama5d4_h32mx_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw);
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u32 mckr = 0;
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if (parent_rate != rate && (parent_rate / 2) != rate)
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return -EINVAL;
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if ((parent_rate / 2) == rate)
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mckr = AT91_PMC_H32MXDIV;
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regmap_update_bits(h32mxclk->regmap, AT91_PMC_MCKR,
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AT91_PMC_H32MXDIV, mckr);
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return 0;
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}
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static const struct clk_ops h32mx_ops = {
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.recalc_rate = clk_sama5d4_h32mx_recalc_rate,
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.round_rate = clk_sama5d4_h32mx_round_rate,
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.set_rate = clk_sama5d4_h32mx_set_rate,
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};
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struct clk_hw * __init
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at91_clk_register_h32mx(struct regmap *regmap, const char *name,
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const char *parent_name)
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{
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struct clk_sama5d4_h32mx *h32mxclk;
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struct clk_init_data init;
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int ret;
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h32mxclk = kzalloc(sizeof(*h32mxclk), GFP_KERNEL);
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if (!h32mxclk)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &h32mx_ops;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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init.flags = CLK_SET_RATE_GATE;
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h32mxclk->hw.init = &init;
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h32mxclk->regmap = regmap;
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ret = clk_hw_register(NULL, &h32mxclk->hw);
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if (ret) {
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kfree(h32mxclk);
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return ERR_PTR(ret);
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}
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return &h32mxclk->hw;
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}
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