// SPDX-License-Identifier: GPL-2.0+
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//
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// OWL common clock driver
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//
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// Copyright (c) 2014 Actions Semi Inc.
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// Author: David Liu <liuwei@actions-semi.com>
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//
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// Copyright (c) 2018 Linaro Ltd.
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// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include "owl-common.h"
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static const struct regmap_config owl_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x00cc,
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.fast_io = true,
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};
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static void owl_clk_set_regmap(const struct owl_clk_desc *desc,
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struct regmap *regmap)
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{
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int i;
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struct owl_clk_common *clks;
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for (i = 0; i < desc->num_clks; i++) {
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clks = desc->clks[i];
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if (!clks)
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continue;
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clks->regmap = regmap;
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}
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}
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int owl_clk_regmap_init(struct platform_device *pdev,
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struct owl_clk_desc *desc)
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{
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void __iomem *base;
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struct regmap *regmap;
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struct resource *res;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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regmap = devm_regmap_init_mmio(&pdev->dev, base, &owl_regmap_config);
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if (IS_ERR(regmap)) {
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pr_err("failed to init regmap\n");
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return PTR_ERR(regmap);
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}
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owl_clk_set_regmap(desc, regmap);
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desc->regmap = regmap;
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return 0;
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}
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int owl_clk_probe(struct device *dev, struct clk_hw_onecell_data *hw_clks)
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{
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int i, ret;
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struct clk_hw *hw;
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for (i = 0; i < hw_clks->num; i++) {
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const char *name;
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hw = hw_clks->hws[i];
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if (IS_ERR_OR_NULL(hw))
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continue;
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name = hw->init->name;
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ret = devm_clk_hw_register(dev, hw);
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if (ret) {
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dev_err(dev, "Couldn't register clock %d - %s\n",
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i, name);
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return ret;
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}
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}
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ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_clks);
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if (ret)
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dev_err(dev, "Failed to add clock provider\n");
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return ret;
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}
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