/* SPDX-License-Identifier: GPL-2.0+ WITH GCC-exception-2.0
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Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
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2004, 2005, 2006
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Free Software Foundation, Inc.
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*/
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!! libgcc routines for the Renesas / SuperH SH CPUs.
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!! Contributed by Steve Chamberlain.
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!! sac@cygnus.com
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!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
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!! recoded in assembly by Toshiyasu Morita
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!! tm@netcom.com
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/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
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ELF local label prefixes by J"orn Rennecke
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amylaar@cygnus.com */
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!
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! __ashlsi3
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!
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! Entry:
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!
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! r4: Value to shift
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! r5: Shifts
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!
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! Exit:
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!
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! r0: Result
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!
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! Destroys:
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!
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! (none)
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!
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! __ashlsi3_r0
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!
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! Entry:
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!
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! r4: Value to shift
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! r0: Shifts
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!
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! Exit:
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!
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! r0: Result
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!
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! Destroys:
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!
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! (none)
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.global __ashlsi3
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.global __ashlsi3_r0
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.align 2
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__ashlsi3:
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mov r5,r0
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.align 2
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__ashlsi3_r0:
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and #31,r0
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mov.l r4,@-r15
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mov r0,r4
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mova ashlsi3_table,r0
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mov.b @(r0,r4),r4
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add r4,r0
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jmp @r0
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mov.l @r15+,r0
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.align 2
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ashlsi3_table:
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.byte ashlsi3_0-ashlsi3_table
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.byte ashlsi3_1-ashlsi3_table
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.byte ashlsi3_2-ashlsi3_table
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.byte ashlsi3_3-ashlsi3_table
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.byte ashlsi3_4-ashlsi3_table
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.byte ashlsi3_5-ashlsi3_table
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.byte ashlsi3_6-ashlsi3_table
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.byte ashlsi3_7-ashlsi3_table
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.byte ashlsi3_8-ashlsi3_table
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.byte ashlsi3_9-ashlsi3_table
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.byte ashlsi3_10-ashlsi3_table
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.byte ashlsi3_11-ashlsi3_table
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.byte ashlsi3_12-ashlsi3_table
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.byte ashlsi3_13-ashlsi3_table
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.byte ashlsi3_14-ashlsi3_table
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.byte ashlsi3_15-ashlsi3_table
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.byte ashlsi3_16-ashlsi3_table
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.byte ashlsi3_17-ashlsi3_table
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.byte ashlsi3_18-ashlsi3_table
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.byte ashlsi3_19-ashlsi3_table
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.byte ashlsi3_20-ashlsi3_table
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.byte ashlsi3_21-ashlsi3_table
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.byte ashlsi3_22-ashlsi3_table
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.byte ashlsi3_23-ashlsi3_table
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.byte ashlsi3_24-ashlsi3_table
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.byte ashlsi3_25-ashlsi3_table
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.byte ashlsi3_26-ashlsi3_table
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.byte ashlsi3_27-ashlsi3_table
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.byte ashlsi3_28-ashlsi3_table
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.byte ashlsi3_29-ashlsi3_table
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.byte ashlsi3_30-ashlsi3_table
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.byte ashlsi3_31-ashlsi3_table
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ashlsi3_6:
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shll2 r0
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ashlsi3_4:
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shll2 r0
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ashlsi3_2:
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rts
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shll2 r0
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ashlsi3_7:
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shll2 r0
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ashlsi3_5:
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shll2 r0
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ashlsi3_3:
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shll2 r0
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ashlsi3_1:
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rts
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shll r0
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ashlsi3_14:
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shll2 r0
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ashlsi3_12:
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shll2 r0
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ashlsi3_10:
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shll2 r0
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ashlsi3_8:
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rts
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shll8 r0
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ashlsi3_15:
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shll2 r0
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ashlsi3_13:
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shll2 r0
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ashlsi3_11:
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shll2 r0
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ashlsi3_9:
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shll8 r0
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rts
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shll r0
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ashlsi3_22:
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shll2 r0
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ashlsi3_20:
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shll2 r0
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ashlsi3_18:
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shll2 r0
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ashlsi3_16:
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rts
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shll16 r0
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ashlsi3_23:
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shll2 r0
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ashlsi3_21:
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shll2 r0
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ashlsi3_19:
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shll2 r0
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ashlsi3_17:
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shll16 r0
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rts
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shll r0
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ashlsi3_30:
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shll2 r0
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ashlsi3_28:
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shll2 r0
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ashlsi3_26:
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shll2 r0
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ashlsi3_24:
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shll16 r0
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rts
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shll8 r0
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ashlsi3_31:
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shll2 r0
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ashlsi3_29:
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shll2 r0
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ashlsi3_27:
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shll2 r0
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ashlsi3_25:
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shll16 r0
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shll8 r0
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rts
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shll r0
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ashlsi3_0:
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rts
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nop
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