/* SPDX-License-Identifier: GPL-2.0
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*
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* include/asm-sh/spinlock-cas.h
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*
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* Copyright (C) 2015 SEI
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*/
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#ifndef __ASM_SH_SPINLOCK_CAS_H
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#define __ASM_SH_SPINLOCK_CAS_H
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#include <asm/barrier.h>
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#include <asm/processor.h>
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static inline unsigned __sl_cas(volatile unsigned *p, unsigned old, unsigned new)
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{
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__asm__ __volatile__("cas.l %1,%0,@r0"
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: "+r"(new)
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: "r"(old), "z"(p)
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: "t", "memory" );
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return new;
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}
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/*
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* Your basic SMP spinlocks, allowing only a single CPU anywhere
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*/
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#define arch_spin_is_locked(x) ((x)->lock <= 0)
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static inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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while (!__sl_cas(&lock->lock, 1, 0));
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}
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static inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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__sl_cas(&lock->lock, 0, 1);
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}
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static inline int arch_spin_trylock(arch_spinlock_t *lock)
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{
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return __sl_cas(&lock->lock, 1, 0);
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}
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/*
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* Read-write spinlocks, allowing multiple readers but only one writer.
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*
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* NOTE! it is quite common to have readers in interrupts but no interrupt
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* writers. For those circumstances we can "mix" irq-safe locks - any writer
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* needs to get a irq-safe write-lock, but readers can get non-irqsafe
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* read-locks.
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*/
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static inline void arch_read_lock(arch_rwlock_t *rw)
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{
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unsigned old;
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do old = rw->lock;
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while (!old || __sl_cas(&rw->lock, old, old-1) != old);
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}
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static inline void arch_read_unlock(arch_rwlock_t *rw)
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{
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unsigned old;
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do old = rw->lock;
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while (__sl_cas(&rw->lock, old, old+1) != old);
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}
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static inline void arch_write_lock(arch_rwlock_t *rw)
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{
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while (__sl_cas(&rw->lock, RW_LOCK_BIAS, 0) != RW_LOCK_BIAS);
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}
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static inline void arch_write_unlock(arch_rwlock_t *rw)
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{
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__sl_cas(&rw->lock, 0, RW_LOCK_BIAS);
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}
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static inline int arch_read_trylock(arch_rwlock_t *rw)
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{
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unsigned old;
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do old = rw->lock;
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while (old && __sl_cas(&rw->lock, old, old-1) != old);
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return !!old;
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}
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static inline int arch_write_trylock(arch_rwlock_t *rw)
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{
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return __sl_cas(&rw->lock, RW_LOCK_BIAS, 0) == RW_LOCK_BIAS;
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}
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#endif /* __ASM_SH_SPINLOCK_CAS_H */
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