/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright IBM Corp. 1999, 2009
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*
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* Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
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*/
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#ifndef __ASM_BARRIER_H
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#define __ASM_BARRIER_H
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/*
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* Force strict CPU ordering.
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* And yes, this is required on UP too when we're talking
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* to devices.
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*/
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#ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
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/* Fast-BCR without checkpoint synchronization */
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#define __ASM_BARRIER "bcr 14,0\n"
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#else
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#define __ASM_BARRIER "bcr 15,0\n"
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#endif
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#define mb() do { asm volatile(__ASM_BARRIER : : : "memory"); } while (0)
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#define rmb() barrier()
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#define wmb() barrier()
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#define dma_rmb() mb()
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#define dma_wmb() mb()
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#define __smp_mb() mb()
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#define __smp_rmb() rmb()
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#define __smp_wmb() wmb()
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#define __smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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barrier(); \
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WRITE_ONCE(*p, v); \
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} while (0)
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#define __smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = READ_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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barrier(); \
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___p1; \
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})
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#define __smp_mb__before_atomic() barrier()
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#define __smp_mb__after_atomic() barrier()
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/**
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* array_index_mask_nospec - generate a mask for array_idx() that is
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* ~0UL when the bounds check succeeds and 0 otherwise
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* @index: array element index
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* @size: number of elements in array
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*/
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#define array_index_mask_nospec array_index_mask_nospec
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static inline unsigned long array_index_mask_nospec(unsigned long index,
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unsigned long size)
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{
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unsigned long mask;
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if (__builtin_constant_p(size) && size > 0) {
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asm(" clgr %2,%1\n"
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" slbgr %0,%0\n"
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:"=d" (mask) : "d" (size-1), "d" (index) :"cc");
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return mask;
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}
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asm(" clgr %1,%2\n"
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" slbgr %0,%0\n"
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:"=d" (mask) : "d" (size), "d" (index) :"cc");
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return ~mask;
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}
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#include <asm-generic/barrier.h>
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#endif /* __ASM_BARRIER_H */
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