/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_TIMEX_H
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#define _ASM_RISCV_TIMEX_H
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#include <asm/csr.h>
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typedef unsigned long cycles_t;
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#ifdef CONFIG_RISCV_M_MODE
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#include <asm/clint.h>
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#ifdef CONFIG_64BIT
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static inline cycles_t get_cycles(void)
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{
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return readq_relaxed(clint_time_val);
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}
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#else /* !CONFIG_64BIT */
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static inline u32 get_cycles(void)
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{
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return readl_relaxed(((u32 *)clint_time_val));
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}
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#define get_cycles get_cycles
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static inline u32 get_cycles_hi(void)
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{
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return readl_relaxed(((u32 *)clint_time_val) + 1);
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}
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#define get_cycles_hi get_cycles_hi
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#endif /* CONFIG_64BIT */
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/*
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* Much like MIPS, we may not have a viable counter to use at an early point
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* in the boot process. Unfortunately we don't have a fallback, so instead
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* we just return 0.
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*/
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static inline unsigned long random_get_entropy(void)
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{
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if (unlikely(clint_time_val == NULL))
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return random_get_entropy_fallback();
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return get_cycles();
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}
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#define random_get_entropy() random_get_entropy()
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#else /* CONFIG_RISCV_M_MODE */
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static inline cycles_t get_cycles(void)
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{
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return csr_read(CSR_TIME);
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}
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#define get_cycles get_cycles
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static inline u32 get_cycles_hi(void)
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{
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return csr_read(CSR_TIMEH);
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}
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#define get_cycles_hi get_cycles_hi
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#endif /* !CONFIG_RISCV_M_MODE */
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#ifdef CONFIG_64BIT
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static inline u64 get_cycles64(void)
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{
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return get_cycles();
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}
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#else /* CONFIG_64BIT */
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static inline u64 get_cycles64(void)
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{
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u32 hi, lo;
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do {
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hi = get_cycles_hi();
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lo = get_cycles();
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} while (hi != get_cycles_hi());
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return ((u64)hi << 32) | lo;
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}
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#endif /* CONFIG_64BIT */
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#define ARCH_HAS_READ_CURRENT_TIMER
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static inline int read_current_timer(unsigned long *timer_val)
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{
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*timer_val = get_cycles();
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return 0;
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}
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#endif /* _ASM_RISCV_TIMEX_H */
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