/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __PPC_FSL_SOC_H
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#define __PPC_FSL_SOC_H
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#ifdef __KERNEL__
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#include <asm/mmu.h>
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struct spi_device;
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extern phys_addr_t get_immrbase(void);
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#if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE)
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extern u32 get_brgfreq(void);
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extern u32 get_baudrate(void);
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#else
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static inline u32 get_brgfreq(void) { return -1; }
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static inline u32 get_baudrate(void) { return -1; }
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#endif
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extern u32 fsl_get_sys_freq(void);
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struct spi_board_info;
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struct device_node;
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/* The different ports that the DIU can be connected to */
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enum fsl_diu_monitor_port {
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FSL_DIU_PORT_DVI, /* DVI */
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FSL_DIU_PORT_LVDS, /* Single-link LVDS */
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FSL_DIU_PORT_DLVDS /* Dual-link LVDS */
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};
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struct platform_diu_data_ops {
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u32 (*get_pixel_format)(enum fsl_diu_monitor_port port,
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unsigned int bpp);
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void (*set_gamma_table)(enum fsl_diu_monitor_port port,
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char *gamma_table_base);
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void (*set_monitor_port)(enum fsl_diu_monitor_port port);
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void (*set_pixel_clock)(unsigned int pixclock);
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enum fsl_diu_monitor_port (*valid_monitor_port)
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(enum fsl_diu_monitor_port port);
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void (*release_bootmem)(void);
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};
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extern struct platform_diu_data_ops diu_ops;
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void __noreturn fsl_hv_restart(char *cmd);
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void __noreturn fsl_hv_halt(void);
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#endif
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#endif
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