// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* PowerPC64 SLB support.
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*
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* Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
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* Based on earlier code written by:
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* Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
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* Copyright (c) 2001 Dave Engebretsen
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* Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
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*/
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#include <asm/asm-prototypes.h>
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#include <asm/mmu.h>
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#include <asm/mmu_context.h>
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#include <asm/paca.h>
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#include <asm/lppaca.h>
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#include <asm/ppc-opcode.h>
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#include <asm/cputable.h>
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#include <asm/cacheflush.h>
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#include <asm/smp.h>
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#include <linux/compiler.h>
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#include <linux/context_tracking.h>
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#include <linux/mm_types.h>
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#include <linux/pgtable.h>
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#include <asm/udbg.h>
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#include <asm/code-patching.h>
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#include "internal.h"
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enum slb_index {
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LINEAR_INDEX = 0, /* Kernel linear map (0xc000000000000000) */
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KSTACK_INDEX = 1, /* Kernel stack map */
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};
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static long slb_allocate_user(struct mm_struct *mm, unsigned long ea);
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#define slb_esid_mask(ssize) \
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(((ssize) == MMU_SEGSIZE_256M)? ESID_MASK: ESID_MASK_1T)
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static inline unsigned long mk_esid_data(unsigned long ea, int ssize,
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enum slb_index index)
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{
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return (ea & slb_esid_mask(ssize)) | SLB_ESID_V | index;
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}
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static inline unsigned long __mk_vsid_data(unsigned long vsid, int ssize,
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unsigned long flags)
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{
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return (vsid << slb_vsid_shift(ssize)) | flags |
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((unsigned long) ssize << SLB_VSID_SSIZE_SHIFT);
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}
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static inline unsigned long mk_vsid_data(unsigned long ea, int ssize,
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unsigned long flags)
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{
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return __mk_vsid_data(get_kernel_vsid(ea, ssize), ssize, flags);
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}
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bool stress_slb_enabled __initdata;
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static int __init parse_stress_slb(char *p)
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{
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stress_slb_enabled = true;
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return 0;
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}
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early_param("stress_slb", parse_stress_slb);
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__ro_after_init DEFINE_STATIC_KEY_FALSE(stress_slb_key);
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static void assert_slb_presence(bool present, unsigned long ea)
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{
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#ifdef CONFIG_DEBUG_VM
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unsigned long tmp;
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WARN_ON_ONCE(mfmsr() & MSR_EE);
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if (!cpu_has_feature(CPU_FTR_ARCH_206))
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return;
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/*
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* slbfee. requires bit 24 (PPC bit 39) be clear in RB. Hardware
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* ignores all other bits from 0-27, so just clear them all.
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*/
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ea &= ~((1UL << SID_SHIFT) - 1);
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asm volatile(__PPC_SLBFEE_DOT(%0, %1) : "=r"(tmp) : "r"(ea) : "cr0");
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WARN_ON(present == (tmp == 0));
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#endif
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}
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static inline void slb_shadow_update(unsigned long ea, int ssize,
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unsigned long flags,
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enum slb_index index)
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{
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struct slb_shadow *p = get_slb_shadow();
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/*
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* Clear the ESID first so the entry is not valid while we are
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* updating it. No write barriers are needed here, provided
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* we only update the current CPU's SLB shadow buffer.
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*/
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WRITE_ONCE(p->save_area[index].esid, 0);
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WRITE_ONCE(p->save_area[index].vsid, cpu_to_be64(mk_vsid_data(ea, ssize, flags)));
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WRITE_ONCE(p->save_area[index].esid, cpu_to_be64(mk_esid_data(ea, ssize, index)));
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}
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static inline void slb_shadow_clear(enum slb_index index)
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{
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WRITE_ONCE(get_slb_shadow()->save_area[index].esid, cpu_to_be64(index));
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}
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static inline void create_shadowed_slbe(unsigned long ea, int ssize,
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unsigned long flags,
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enum slb_index index)
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{
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/*
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* Updating the shadow buffer before writing the SLB ensures
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* we don't get a stale entry here if we get preempted by PHYP
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* between these two statements.
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*/
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slb_shadow_update(ea, ssize, flags, index);
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assert_slb_presence(false, ea);
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asm volatile("slbmte %0,%1" :
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: "r" (mk_vsid_data(ea, ssize, flags)),
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"r" (mk_esid_data(ea, ssize, index))
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: "memory" );
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}
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/*
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* Insert bolted entries into SLB (which may not be empty, so don't clear
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* slb_cache_ptr).
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*/
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void __slb_restore_bolted_realmode(void)
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{
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struct slb_shadow *p = get_slb_shadow();
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enum slb_index index;
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/* No isync needed because realmode. */
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for (index = 0; index < SLB_NUM_BOLTED; index++) {
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asm volatile("slbmte %0,%1" :
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: "r" (be64_to_cpu(p->save_area[index].vsid)),
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"r" (be64_to_cpu(p->save_area[index].esid)));
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}
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assert_slb_presence(true, local_paca->kstack);
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}
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/*
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* Insert the bolted entries into an empty SLB.
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*/
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void slb_restore_bolted_realmode(void)
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{
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__slb_restore_bolted_realmode();
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get_paca()->slb_cache_ptr = 0;
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get_paca()->slb_kern_bitmap = (1U << SLB_NUM_BOLTED) - 1;
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get_paca()->slb_used_bitmap = get_paca()->slb_kern_bitmap;
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}
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/*
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* This flushes all SLB entries including 0, so it must be realmode.
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*/
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void slb_flush_all_realmode(void)
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{
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asm volatile("slbmte %0,%0; slbia" : : "r" (0));
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}
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static __always_inline void __slb_flush_and_restore_bolted(bool preserve_kernel_lookaside)
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{
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struct slb_shadow *p = get_slb_shadow();
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unsigned long ksp_esid_data, ksp_vsid_data;
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u32 ih;
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/*
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* SLBIA IH=1 on ISA v2.05 and newer processors may preserve lookaside
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* information created with Class=0 entries, which we use for kernel
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* SLB entries (the SLB entries themselves are still invalidated).
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*
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* Older processors will ignore this optimisation. Over-invalidation
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* is fine because we never rely on lookaside information existing.
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*/
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if (preserve_kernel_lookaside)
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ih = 1;
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else
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ih = 0;
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ksp_esid_data = be64_to_cpu(p->save_area[KSTACK_INDEX].esid);
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ksp_vsid_data = be64_to_cpu(p->save_area[KSTACK_INDEX].vsid);
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asm volatile(PPC_SLBIA(%0)" \n"
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"slbmte %1, %2 \n"
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:: "i" (ih),
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"r" (ksp_vsid_data),
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"r" (ksp_esid_data)
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: "memory");
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}
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/*
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* This flushes non-bolted entries, it can be run in virtual mode. Must
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* be called with interrupts disabled.
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*/
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void slb_flush_and_restore_bolted(void)
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{
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BUILD_BUG_ON(SLB_NUM_BOLTED != 2);
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WARN_ON(!irqs_disabled());
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/*
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* We can't take a PMU exception in the following code, so hard
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* disable interrupts.
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*/
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hard_irq_disable();
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isync();
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__slb_flush_and_restore_bolted(false);
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isync();
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assert_slb_presence(true, get_paca()->kstack);
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get_paca()->slb_cache_ptr = 0;
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get_paca()->slb_kern_bitmap = (1U << SLB_NUM_BOLTED) - 1;
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get_paca()->slb_used_bitmap = get_paca()->slb_kern_bitmap;
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}
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void slb_save_contents(struct slb_entry *slb_ptr)
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{
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int i;
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unsigned long e, v;
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/* Save slb_cache_ptr value. */
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get_paca()->slb_save_cache_ptr = get_paca()->slb_cache_ptr;
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if (!slb_ptr)
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return;
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for (i = 0; i < mmu_slb_size; i++) {
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asm volatile("slbmfee %0,%1" : "=r" (e) : "r" (i));
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asm volatile("slbmfev %0,%1" : "=r" (v) : "r" (i));
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slb_ptr->esid = e;
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slb_ptr->vsid = v;
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slb_ptr++;
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}
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}
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void slb_dump_contents(struct slb_entry *slb_ptr)
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{
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int i, n;
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unsigned long e, v;
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unsigned long llp;
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if (!slb_ptr)
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return;
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pr_err("SLB contents of cpu 0x%x\n", smp_processor_id());
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pr_err("Last SLB entry inserted at slot %d\n", get_paca()->stab_rr);
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for (i = 0; i < mmu_slb_size; i++) {
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e = slb_ptr->esid;
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v = slb_ptr->vsid;
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slb_ptr++;
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if (!e && !v)
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continue;
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pr_err("%02d %016lx %016lx\n", i, e, v);
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if (!(e & SLB_ESID_V)) {
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pr_err("\n");
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continue;
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}
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llp = v & SLB_VSID_LLP;
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if (v & SLB_VSID_B_1T) {
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pr_err(" 1T ESID=%9lx VSID=%13lx LLP:%3lx\n",
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GET_ESID_1T(e),
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(v & ~SLB_VSID_B) >> SLB_VSID_SHIFT_1T, llp);
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} else {
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pr_err(" 256M ESID=%9lx VSID=%13lx LLP:%3lx\n",
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GET_ESID(e),
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(v & ~SLB_VSID_B) >> SLB_VSID_SHIFT, llp);
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}
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}
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pr_err("----------------------------------\n");
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/* Dump slb cache entires as well. */
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pr_err("SLB cache ptr value = %d\n", get_paca()->slb_save_cache_ptr);
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pr_err("Valid SLB cache entries:\n");
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n = min_t(int, get_paca()->slb_save_cache_ptr, SLB_CACHE_ENTRIES);
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for (i = 0; i < n; i++)
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pr_err("%02d EA[0-35]=%9x\n", i, get_paca()->slb_cache[i]);
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pr_err("Rest of SLB cache entries:\n");
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for (i = n; i < SLB_CACHE_ENTRIES; i++)
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pr_err("%02d EA[0-35]=%9x\n", i, get_paca()->slb_cache[i]);
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}
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void slb_vmalloc_update(void)
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{
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/*
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* vmalloc is not bolted, so just have to flush non-bolted.
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*/
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slb_flush_and_restore_bolted();
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}
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static bool preload_hit(struct thread_info *ti, unsigned long esid)
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{
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unsigned char i;
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for (i = 0; i < ti->slb_preload_nr; i++) {
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unsigned char idx;
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idx = (ti->slb_preload_tail + i) % SLB_PRELOAD_NR;
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if (esid == ti->slb_preload_esid[idx])
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return true;
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}
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return false;
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}
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static bool preload_add(struct thread_info *ti, unsigned long ea)
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{
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unsigned char idx;
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unsigned long esid;
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if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
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/* EAs are stored >> 28 so 256MB segments don't need clearing */
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if (ea & ESID_MASK_1T)
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ea &= ESID_MASK_1T;
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}
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esid = ea >> SID_SHIFT;
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if (preload_hit(ti, esid))
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return false;
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idx = (ti->slb_preload_tail + ti->slb_preload_nr) % SLB_PRELOAD_NR;
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ti->slb_preload_esid[idx] = esid;
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if (ti->slb_preload_nr == SLB_PRELOAD_NR)
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ti->slb_preload_tail = (ti->slb_preload_tail + 1) % SLB_PRELOAD_NR;
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else
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ti->slb_preload_nr++;
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return true;
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}
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static void preload_age(struct thread_info *ti)
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{
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if (!ti->slb_preload_nr)
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return;
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ti->slb_preload_nr--;
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ti->slb_preload_tail = (ti->slb_preload_tail + 1) % SLB_PRELOAD_NR;
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}
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void slb_setup_new_exec(void)
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{
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struct thread_info *ti = current_thread_info();
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struct mm_struct *mm = current->mm;
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unsigned long exec = 0x10000000;
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WARN_ON(irqs_disabled());
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/*
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* preload cache can only be used to determine whether a SLB
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* entry exists if it does not start to overflow.
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*/
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if (ti->slb_preload_nr + 2 > SLB_PRELOAD_NR)
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return;
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hard_irq_disable();
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/*
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* We have no good place to clear the slb preload cache on exec,
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* flush_thread is about the earliest arch hook but that happens
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* after we switch to the mm and have aleady preloaded the SLBEs.
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*
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* For the most part that's probably okay to use entries from the
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* previous exec, they will age out if unused. It may turn out to
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* be an advantage to clear the cache before switching to it,
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* however.
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*/
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/*
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* preload some userspace segments into the SLB.
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* Almost all 32 and 64bit PowerPC executables are linked at
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* 0x10000000 so it makes sense to preload this segment.
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*/
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if (!is_kernel_addr(exec)) {
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if (preload_add(ti, exec))
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slb_allocate_user(mm, exec);
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}
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/* Libraries and mmaps. */
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if (!is_kernel_addr(mm->mmap_base)) {
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if (preload_add(ti, mm->mmap_base))
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slb_allocate_user(mm, mm->mmap_base);
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}
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/* see switch_slb */
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asm volatile("isync" : : : "memory");
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local_irq_enable();
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}
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void preload_new_slb_context(unsigned long start, unsigned long sp)
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{
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struct thread_info *ti = current_thread_info();
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struct mm_struct *mm = current->mm;
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unsigned long heap = mm->start_brk;
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WARN_ON(irqs_disabled());
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/* see above */
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if (ti->slb_preload_nr + 3 > SLB_PRELOAD_NR)
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return;
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hard_irq_disable();
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/* Userspace entry address. */
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if (!is_kernel_addr(start)) {
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if (preload_add(ti, start))
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slb_allocate_user(mm, start);
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}
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/* Top of stack, grows down. */
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if (!is_kernel_addr(sp)) {
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if (preload_add(ti, sp))
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slb_allocate_user(mm, sp);
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}
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/* Bottom of heap, grows up. */
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if (heap && !is_kernel_addr(heap)) {
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if (preload_add(ti, heap))
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slb_allocate_user(mm, heap);
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}
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/* see switch_slb */
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asm volatile("isync" : : : "memory");
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local_irq_enable();
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}
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static void slb_cache_slbie_kernel(unsigned int index)
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{
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unsigned long slbie_data = get_paca()->slb_cache[index];
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unsigned long ksp = get_paca()->kstack;
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slbie_data <<= SID_SHIFT;
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slbie_data |= 0xc000000000000000ULL;
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if ((ksp & slb_esid_mask(mmu_kernel_ssize)) == slbie_data)
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return;
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slbie_data |= mmu_kernel_ssize << SLBIE_SSIZE_SHIFT;
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asm volatile("slbie %0" : : "r" (slbie_data));
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}
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static void slb_cache_slbie_user(unsigned int index)
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{
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unsigned long slbie_data = get_paca()->slb_cache[index];
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slbie_data <<= SID_SHIFT;
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slbie_data |= user_segment_size(slbie_data) << SLBIE_SSIZE_SHIFT;
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slbie_data |= SLBIE_C; /* user slbs have C=1 */
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asm volatile("slbie %0" : : "r" (slbie_data));
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}
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/* Flush all user entries from the segment table of the current processor. */
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void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
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{
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struct thread_info *ti = task_thread_info(tsk);
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unsigned char i;
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/*
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* We need interrupts hard-disabled here, not just soft-disabled,
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* so that a PMU interrupt can't occur, which might try to access
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* user memory (to get a stack trace) and possible cause an SLB miss
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* which would update the slb_cache/slb_cache_ptr fields in the PACA.
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*/
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hard_irq_disable();
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isync();
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if (stress_slb()) {
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__slb_flush_and_restore_bolted(false);
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isync();
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get_paca()->slb_cache_ptr = 0;
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get_paca()->slb_kern_bitmap = (1U << SLB_NUM_BOLTED) - 1;
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} else if (cpu_has_feature(CPU_FTR_ARCH_300)) {
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/*
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* SLBIA IH=3 invalidates all Class=1 SLBEs and their
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* associated lookaside structures, which matches what
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* switch_slb wants. So ARCH_300 does not use the slb
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* cache.
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*/
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asm volatile(PPC_SLBIA(3));
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} else {
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unsigned long offset = get_paca()->slb_cache_ptr;
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if (!mmu_has_feature(MMU_FTR_NO_SLBIE_B) &&
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offset <= SLB_CACHE_ENTRIES) {
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/*
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* Could assert_slb_presence(true) here, but
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* hypervisor or machine check could have come
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* in and removed the entry at this point.
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*/
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for (i = 0; i < offset; i++)
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slb_cache_slbie_user(i);
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/* Workaround POWER5 < DD2.1 issue */
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if (!cpu_has_feature(CPU_FTR_ARCH_207S) && offset == 1)
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slb_cache_slbie_user(0);
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} else {
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/* Flush but retain kernel lookaside information */
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__slb_flush_and_restore_bolted(true);
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isync();
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get_paca()->slb_kern_bitmap = (1U << SLB_NUM_BOLTED) - 1;
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}
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get_paca()->slb_cache_ptr = 0;
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}
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get_paca()->slb_used_bitmap = get_paca()->slb_kern_bitmap;
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copy_mm_to_paca(mm);
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/*
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* We gradually age out SLBs after a number of context switches to
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* reduce reload overhead of unused entries (like we do with FP/VEC
|
* reload). Each time we wrap 256 switches, take an entry out of the
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* SLB preload cache.
|
*/
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tsk->thread.load_slb++;
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if (!tsk->thread.load_slb) {
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unsigned long pc = KSTK_EIP(tsk);
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preload_age(ti);
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preload_add(ti, pc);
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}
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for (i = 0; i < ti->slb_preload_nr; i++) {
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unsigned char idx;
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unsigned long ea;
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idx = (ti->slb_preload_tail + i) % SLB_PRELOAD_NR;
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ea = (unsigned long)ti->slb_preload_esid[idx] << SID_SHIFT;
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slb_allocate_user(mm, ea);
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}
|
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/*
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* Synchronize slbmte preloads with possible subsequent user memory
|
* address accesses by the kernel (user mode won't happen until
|
* rfid, which is safe).
|
*/
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isync();
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}
|
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void slb_set_size(u16 size)
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{
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mmu_slb_size = size;
|
}
|
|
void slb_initialize(void)
|
{
|
unsigned long linear_llp, vmalloc_llp, io_llp;
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unsigned long lflags;
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static int slb_encoding_inited;
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#ifdef CONFIG_SPARSEMEM_VMEMMAP
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unsigned long vmemmap_llp;
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#endif
|
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/* Prepare our SLB miss handler based on our page size */
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linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
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io_llp = mmu_psize_defs[mmu_io_psize].sllp;
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vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp;
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get_paca()->vmalloc_sllp = SLB_VSID_KERNEL | vmalloc_llp;
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#ifdef CONFIG_SPARSEMEM_VMEMMAP
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vmemmap_llp = mmu_psize_defs[mmu_vmemmap_psize].sllp;
|
#endif
|
if (!slb_encoding_inited) {
|
slb_encoding_inited = 1;
|
pr_devel("SLB: linear LLP = %04lx\n", linear_llp);
|
pr_devel("SLB: io LLP = %04lx\n", io_llp);
|
#ifdef CONFIG_SPARSEMEM_VMEMMAP
|
pr_devel("SLB: vmemmap LLP = %04lx\n", vmemmap_llp);
|
#endif
|
}
|
|
get_paca()->stab_rr = SLB_NUM_BOLTED - 1;
|
get_paca()->slb_kern_bitmap = (1U << SLB_NUM_BOLTED) - 1;
|
get_paca()->slb_used_bitmap = get_paca()->slb_kern_bitmap;
|
|
lflags = SLB_VSID_KERNEL | linear_llp;
|
|
/* Invalidate the entire SLB (even entry 0) & all the ERATS */
|
asm volatile("isync":::"memory");
|
asm volatile("slbmte %0,%0"::"r" (0) : "memory");
|
asm volatile("isync; slbia; isync":::"memory");
|
create_shadowed_slbe(PAGE_OFFSET, mmu_kernel_ssize, lflags, LINEAR_INDEX);
|
|
/*
|
* For the boot cpu, we're running on the stack in init_thread_union,
|
* which is in the first segment of the linear mapping, and also
|
* get_paca()->kstack hasn't been initialized yet.
|
* For secondary cpus, we need to bolt the kernel stack entry now.
|
*/
|
slb_shadow_clear(KSTACK_INDEX);
|
if (raw_smp_processor_id() != boot_cpuid &&
|
(get_paca()->kstack & slb_esid_mask(mmu_kernel_ssize)) > PAGE_OFFSET)
|
create_shadowed_slbe(get_paca()->kstack,
|
mmu_kernel_ssize, lflags, KSTACK_INDEX);
|
|
asm volatile("isync":::"memory");
|
}
|
|
static void slb_cache_update(unsigned long esid_data)
|
{
|
int slb_cache_index;
|
|
if (cpu_has_feature(CPU_FTR_ARCH_300))
|
return; /* ISAv3.0B and later does not use slb_cache */
|
|
if (stress_slb())
|
return;
|
|
/*
|
* Now update slb cache entries
|
*/
|
slb_cache_index = local_paca->slb_cache_ptr;
|
if (slb_cache_index < SLB_CACHE_ENTRIES) {
|
/*
|
* We have space in slb cache for optimized switch_slb().
|
* Top 36 bits from esid_data as per ISA
|
*/
|
local_paca->slb_cache[slb_cache_index++] = esid_data >> SID_SHIFT;
|
local_paca->slb_cache_ptr++;
|
} else {
|
/*
|
* Our cache is full and the current cache content strictly
|
* doesn't indicate the active SLB conents. Bump the ptr
|
* so that switch_slb() will ignore the cache.
|
*/
|
local_paca->slb_cache_ptr = SLB_CACHE_ENTRIES + 1;
|
}
|
}
|
|
static enum slb_index alloc_slb_index(bool kernel)
|
{
|
enum slb_index index;
|
|
/*
|
* The allocation bitmaps can become out of synch with the SLB
|
* when the _switch code does slbie when bolting a new stack
|
* segment and it must not be anywhere else in the SLB. This leaves
|
* a kernel allocated entry that is unused in the SLB. With very
|
* large systems or small segment sizes, the bitmaps could slowly
|
* fill with these entries. They will eventually be cleared out
|
* by the round robin allocator in that case, so it's probably not
|
* worth accounting for.
|
*/
|
|
/*
|
* SLBs beyond 32 entries are allocated with stab_rr only
|
* POWER7/8/9 have 32 SLB entries, this could be expanded if a
|
* future CPU has more.
|
*/
|
if (local_paca->slb_used_bitmap != U32_MAX) {
|
index = ffz(local_paca->slb_used_bitmap);
|
local_paca->slb_used_bitmap |= 1U << index;
|
if (kernel)
|
local_paca->slb_kern_bitmap |= 1U << index;
|
} else {
|
/* round-robin replacement of slb starting at SLB_NUM_BOLTED. */
|
index = local_paca->stab_rr;
|
if (index < (mmu_slb_size - 1))
|
index++;
|
else
|
index = SLB_NUM_BOLTED;
|
local_paca->stab_rr = index;
|
if (index < 32) {
|
if (kernel)
|
local_paca->slb_kern_bitmap |= 1U << index;
|
else
|
local_paca->slb_kern_bitmap &= ~(1U << index);
|
}
|
}
|
BUG_ON(index < SLB_NUM_BOLTED);
|
|
return index;
|
}
|
|
static long slb_insert_entry(unsigned long ea, unsigned long context,
|
unsigned long flags, int ssize, bool kernel)
|
{
|
unsigned long vsid;
|
unsigned long vsid_data, esid_data;
|
enum slb_index index;
|
|
vsid = get_vsid(context, ea, ssize);
|
if (!vsid)
|
return -EFAULT;
|
|
/*
|
* There must not be a kernel SLB fault in alloc_slb_index or before
|
* slbmte here or the allocation bitmaps could get out of whack with
|
* the SLB.
|
*
|
* User SLB faults or preloads take this path which might get inlined
|
* into the caller, so add compiler barriers here to ensure unsafe
|
* memory accesses do not come between.
|
*/
|
barrier();
|
|
index = alloc_slb_index(kernel);
|
|
vsid_data = __mk_vsid_data(vsid, ssize, flags);
|
esid_data = mk_esid_data(ea, ssize, index);
|
|
/*
|
* No need for an isync before or after this slbmte. The exception
|
* we enter with and the rfid we exit with are context synchronizing.
|
* User preloads should add isync afterwards in case the kernel
|
* accesses user memory before it returns to userspace with rfid.
|
*/
|
assert_slb_presence(false, ea);
|
if (stress_slb()) {
|
int slb_cache_index = local_paca->slb_cache_ptr;
|
|
/*
|
* stress_slb() does not use slb cache, repurpose as a
|
* cache of inserted (non-bolted) kernel SLB entries. All
|
* non-bolted kernel entries are flushed on any user fault,
|
* or if there are already 3 non-boled kernel entries.
|
*/
|
BUILD_BUG_ON(SLB_CACHE_ENTRIES < 3);
|
if (!kernel || slb_cache_index == 3) {
|
int i;
|
|
for (i = 0; i < slb_cache_index; i++)
|
slb_cache_slbie_kernel(i);
|
slb_cache_index = 0;
|
}
|
|
if (kernel)
|
local_paca->slb_cache[slb_cache_index++] = esid_data >> SID_SHIFT;
|
local_paca->slb_cache_ptr = slb_cache_index;
|
}
|
asm volatile("slbmte %0, %1" : : "r" (vsid_data), "r" (esid_data));
|
|
barrier();
|
|
if (!kernel)
|
slb_cache_update(esid_data);
|
|
return 0;
|
}
|
|
static long slb_allocate_kernel(unsigned long ea, unsigned long id)
|
{
|
unsigned long context;
|
unsigned long flags;
|
int ssize;
|
|
if (id == LINEAR_MAP_REGION_ID) {
|
|
/* We only support upto H_MAX_PHYSMEM_BITS */
|
if ((ea & EA_MASK) > (1UL << H_MAX_PHYSMEM_BITS))
|
return -EFAULT;
|
|
flags = SLB_VSID_KERNEL | mmu_psize_defs[mmu_linear_psize].sllp;
|
|
#ifdef CONFIG_SPARSEMEM_VMEMMAP
|
} else if (id == VMEMMAP_REGION_ID) {
|
|
if (ea >= H_VMEMMAP_END)
|
return -EFAULT;
|
|
flags = SLB_VSID_KERNEL | mmu_psize_defs[mmu_vmemmap_psize].sllp;
|
#endif
|
} else if (id == VMALLOC_REGION_ID) {
|
|
if (ea >= H_VMALLOC_END)
|
return -EFAULT;
|
|
flags = local_paca->vmalloc_sllp;
|
|
} else if (id == IO_REGION_ID) {
|
|
if (ea >= H_KERN_IO_END)
|
return -EFAULT;
|
|
flags = SLB_VSID_KERNEL | mmu_psize_defs[mmu_io_psize].sllp;
|
|
} else {
|
return -EFAULT;
|
}
|
|
ssize = MMU_SEGSIZE_1T;
|
if (!mmu_has_feature(MMU_FTR_1T_SEGMENT))
|
ssize = MMU_SEGSIZE_256M;
|
|
context = get_kernel_context(ea);
|
|
return slb_insert_entry(ea, context, flags, ssize, true);
|
}
|
|
static long slb_allocate_user(struct mm_struct *mm, unsigned long ea)
|
{
|
unsigned long context;
|
unsigned long flags;
|
int bpsize;
|
int ssize;
|
|
/*
|
* consider this as bad access if we take a SLB miss
|
* on an address above addr limit.
|
*/
|
if (ea >= mm_ctx_slb_addr_limit(&mm->context))
|
return -EFAULT;
|
|
context = get_user_context(&mm->context, ea);
|
if (!context)
|
return -EFAULT;
|
|
if (unlikely(ea >= H_PGTABLE_RANGE)) {
|
WARN_ON(1);
|
return -EFAULT;
|
}
|
|
ssize = user_segment_size(ea);
|
|
bpsize = get_slice_psize(mm, ea);
|
flags = SLB_VSID_USER | mmu_psize_defs[bpsize].sllp;
|
|
return slb_insert_entry(ea, context, flags, ssize, false);
|
}
|
|
long do_slb_fault(struct pt_regs *regs, unsigned long ea)
|
{
|
unsigned long id = get_region_id(ea);
|
|
/* IRQs are not reconciled here, so can't check irqs_disabled */
|
VM_WARN_ON(mfmsr() & MSR_EE);
|
|
if (unlikely(!(regs->msr & MSR_RI)))
|
return -EINVAL;
|
|
/*
|
* SLB kernel faults must be very careful not to touch anything
|
* that is not bolted. E.g., PACA and global variables are okay,
|
* mm->context stuff is not.
|
*
|
* SLB user faults can access all of kernel memory, but must be
|
* careful not to touch things like IRQ state because it is not
|
* "reconciled" here. The difficulty is that we must use
|
* fast_exception_return to return from kernel SLB faults without
|
* looking at possible non-bolted memory. We could test user vs
|
* kernel faults in the interrupt handler asm and do a full fault,
|
* reconcile, ret_from_except for user faults which would make them
|
* first class kernel code. But for performance it's probably nicer
|
* if they go via fast_exception_return too.
|
*/
|
if (id >= LINEAR_MAP_REGION_ID) {
|
long err;
|
#ifdef CONFIG_DEBUG_VM
|
/* Catch recursive kernel SLB faults. */
|
BUG_ON(local_paca->in_kernel_slb_handler);
|
local_paca->in_kernel_slb_handler = 1;
|
#endif
|
err = slb_allocate_kernel(ea, id);
|
#ifdef CONFIG_DEBUG_VM
|
local_paca->in_kernel_slb_handler = 0;
|
#endif
|
return err;
|
} else {
|
struct mm_struct *mm = current->mm;
|
long err;
|
|
if (unlikely(!mm))
|
return -EFAULT;
|
|
err = slb_allocate_user(mm, ea);
|
if (!err)
|
preload_add(current_thread_info(), ea);
|
|
return err;
|
}
|
}
|
|
void do_bad_slb_fault(struct pt_regs *regs, unsigned long ea, long err)
|
{
|
if (err == -EFAULT) {
|
if (user_mode(regs))
|
_exception(SIGSEGV, regs, SEGV_BNDERR, ea);
|
else
|
bad_page_fault(regs, ea, SIGSEGV);
|
} else if (err == -EINVAL) {
|
unrecoverable_exception(regs);
|
} else {
|
BUG();
|
}
|
}
|
