// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
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*/
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#include <linux/sched.h>
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#include <linux/mm_types.h>
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#include <linux/memblock.h>
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#include <misc/cxl-base.h>
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#include <asm/debugfs.h>
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#include <asm/pgalloc.h>
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#include <asm/tlb.h>
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#include <asm/trace.h>
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#include <asm/powernv.h>
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#include <asm/firmware.h>
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#include <asm/ultravisor.h>
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#include <asm/kexec.h>
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#include <mm/mmu_decl.h>
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#include <trace/events/thp.h>
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unsigned long __pmd_frag_nr;
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EXPORT_SYMBOL(__pmd_frag_nr);
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unsigned long __pmd_frag_size_shift;
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EXPORT_SYMBOL(__pmd_frag_size_shift);
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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/*
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* This is called when relaxing access to a hugepage. It's also called in the page
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* fault path when we don't hit any of the major fault cases, ie, a minor
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* update of _PAGE_ACCESSED, _PAGE_DIRTY, etc... The generic code will have
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* handled those two for us, we additionally deal with missing execute
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* permission here on some processors
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*/
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int pmdp_set_access_flags(struct vm_area_struct *vma, unsigned long address,
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pmd_t *pmdp, pmd_t entry, int dirty)
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{
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int changed;
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#ifdef CONFIG_DEBUG_VM
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WARN_ON(!pmd_trans_huge(*pmdp) && !pmd_devmap(*pmdp));
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assert_spin_locked(pmd_lockptr(vma->vm_mm, pmdp));
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#endif
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changed = !pmd_same(*(pmdp), entry);
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if (changed) {
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/*
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* We can use MMU_PAGE_2M here, because only radix
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* path look at the psize.
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*/
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__ptep_set_access_flags(vma, pmdp_ptep(pmdp),
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pmd_pte(entry), address, MMU_PAGE_2M);
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}
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return changed;
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}
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int pmdp_test_and_clear_young(struct vm_area_struct *vma,
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unsigned long address, pmd_t *pmdp)
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{
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return __pmdp_test_and_clear_young(vma->vm_mm, address, pmdp);
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}
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/*
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* set a new huge pmd. We should not be called for updating
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* an existing pmd entry. That should go via pmd_hugepage_update.
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*/
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void set_pmd_at(struct mm_struct *mm, unsigned long addr,
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pmd_t *pmdp, pmd_t pmd)
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{
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#ifdef CONFIG_DEBUG_VM
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/*
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* Make sure hardware valid bit is not set. We don't do
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* tlb flush for this update.
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*/
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WARN_ON(pte_hw_valid(pmd_pte(*pmdp)) && !pte_protnone(pmd_pte(*pmdp)));
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assert_spin_locked(pmd_lockptr(mm, pmdp));
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WARN_ON(!(pmd_large(pmd)));
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#endif
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trace_hugepage_set_pmd(addr, pmd_val(pmd));
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return set_pte_at(mm, addr, pmdp_ptep(pmdp), pmd_pte(pmd));
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}
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static void do_nothing(void *unused)
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{
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}
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/*
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* Serialize against find_current_mm_pte which does lock-less
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* lookup in page tables with local interrupts disabled. For huge pages
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* it casts pmd_t to pte_t. Since format of pte_t is different from
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* pmd_t we want to prevent transit from pmd pointing to page table
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* to pmd pointing to huge page (and back) while interrupts are disabled.
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* We clear pmd to possibly replace it with page table pointer in
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* different code paths. So make sure we wait for the parallel
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* find_current_mm_pte to finish.
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*/
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void serialize_against_pte_lookup(struct mm_struct *mm)
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{
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smp_mb();
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smp_call_function_many(mm_cpumask(mm), do_nothing, NULL, 1);
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}
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/*
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* We use this to invalidate a pmdp entry before switching from a
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* hugepte to regular pmd entry.
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*/
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pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
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pmd_t *pmdp)
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{
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unsigned long old_pmd;
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old_pmd = pmd_hugepage_update(vma->vm_mm, address, pmdp, _PAGE_PRESENT, _PAGE_INVALID);
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flush_pmd_tlb_range(vma, address, address + HPAGE_PMD_SIZE);
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return __pmd(old_pmd);
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}
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pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma,
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unsigned long addr, pmd_t *pmdp, int full)
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{
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pmd_t pmd;
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VM_BUG_ON(addr & ~HPAGE_PMD_MASK);
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VM_BUG_ON((pmd_present(*pmdp) && !pmd_trans_huge(*pmdp) &&
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!pmd_devmap(*pmdp)) || !pmd_present(*pmdp));
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pmd = pmdp_huge_get_and_clear(vma->vm_mm, addr, pmdp);
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/*
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* if it not a fullmm flush, then we can possibly end up converting
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* this PMD pte entry to a regular level 0 PTE by a parallel page fault.
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* Make sure we flush the tlb in this case.
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*/
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if (!full)
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flush_pmd_tlb_range(vma, addr, addr + HPAGE_PMD_SIZE);
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return pmd;
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}
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static pmd_t pmd_set_protbits(pmd_t pmd, pgprot_t pgprot)
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{
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return __pmd(pmd_val(pmd) | pgprot_val(pgprot));
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}
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pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot)
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{
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unsigned long pmdv;
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pmdv = (pfn << PAGE_SHIFT) & PTE_RPN_MASK;
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return pmd_set_protbits(__pmd(pmdv), pgprot);
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}
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pmd_t mk_pmd(struct page *page, pgprot_t pgprot)
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{
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return pfn_pmd(page_to_pfn(page), pgprot);
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}
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pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
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{
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unsigned long pmdv;
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pmdv = pmd_val(pmd);
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pmdv &= _HPAGE_CHG_MASK;
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return pmd_set_protbits(__pmd(pmdv), newprot);
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}
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#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
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/* For use by kexec */
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void mmu_cleanup_all(void)
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{
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if (radix_enabled())
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radix__mmu_cleanup_all();
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else if (mmu_hash_ops.hpte_clear_all)
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mmu_hash_ops.hpte_clear_all();
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reset_sprs();
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}
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#ifdef CONFIG_MEMORY_HOTPLUG
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int __meminit create_section_mapping(unsigned long start, unsigned long end,
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int nid, pgprot_t prot)
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{
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if (radix_enabled())
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return radix__create_section_mapping(start, end, nid, prot);
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return hash__create_section_mapping(start, end, nid, prot);
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}
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int __meminit remove_section_mapping(unsigned long start, unsigned long end)
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{
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if (radix_enabled())
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return radix__remove_section_mapping(start, end);
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return hash__remove_section_mapping(start, end);
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}
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#endif /* CONFIG_MEMORY_HOTPLUG */
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void __init mmu_partition_table_init(void)
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{
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unsigned long patb_size = 1UL << PATB_SIZE_SHIFT;
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unsigned long ptcr;
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BUILD_BUG_ON_MSG((PATB_SIZE_SHIFT > 36), "Partition table size too large.");
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/* Initialize the Partition Table with no entries */
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partition_tb = memblock_alloc(patb_size, patb_size);
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if (!partition_tb)
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panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
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__func__, patb_size, patb_size);
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/*
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* update partition table control register,
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* 64 K size.
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*/
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ptcr = __pa(partition_tb) | (PATB_SIZE_SHIFT - 12);
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set_ptcr_when_no_uv(ptcr);
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powernv_set_nmmu_ptcr(ptcr);
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}
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static void flush_partition(unsigned int lpid, bool radix)
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{
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if (radix) {
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radix__flush_all_lpid(lpid);
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radix__flush_all_lpid_guest(lpid);
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} else {
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asm volatile("ptesync" : : : "memory");
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asm volatile(PPC_TLBIE_5(%0,%1,2,0,0) : :
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"r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
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/* do we need fixup here ?*/
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asm volatile("eieio; tlbsync; ptesync" : : : "memory");
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trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 0);
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}
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}
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void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,
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unsigned long dw1, bool flush)
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{
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unsigned long old = be64_to_cpu(partition_tb[lpid].patb0);
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/*
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* When ultravisor is enabled, the partition table is stored in secure
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* memory and can only be accessed doing an ultravisor call. However, we
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* maintain a copy of the partition table in normal memory to allow Nest
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* MMU translations to occur (for normal VMs).
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*
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* Therefore, here we always update partition_tb, regardless of whether
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* we are running under an ultravisor or not.
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*/
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partition_tb[lpid].patb0 = cpu_to_be64(dw0);
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partition_tb[lpid].patb1 = cpu_to_be64(dw1);
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/*
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* If ultravisor is enabled, we do an ultravisor call to register the
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* partition table entry (PATE), which also do a global flush of TLBs
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* and partition table caches for the lpid. Otherwise, just do the
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* flush. The type of flush (hash or radix) depends on what the previous
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* use of the partition ID was, not the new use.
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*/
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if (firmware_has_feature(FW_FEATURE_ULTRAVISOR)) {
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uv_register_pate(lpid, dw0, dw1);
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pr_info("PATE registered by ultravisor: dw0 = 0x%lx, dw1 = 0x%lx\n",
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dw0, dw1);
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} else if (flush) {
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/*
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* Boot does not need to flush, because MMU is off and each
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* CPU does a tlbiel_all() before switching them on, which
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* flushes everything.
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*/
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flush_partition(lpid, (old & PATB_HR));
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}
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}
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EXPORT_SYMBOL_GPL(mmu_partition_table_set_entry);
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static pmd_t *get_pmd_from_cache(struct mm_struct *mm)
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{
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void *pmd_frag, *ret;
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if (PMD_FRAG_NR == 1)
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return NULL;
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spin_lock(&mm->page_table_lock);
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ret = mm->context.pmd_frag;
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if (ret) {
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pmd_frag = ret + PMD_FRAG_SIZE;
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/*
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* If we have taken up all the fragments mark PTE page NULL
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*/
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if (((unsigned long)pmd_frag & ~PAGE_MASK) == 0)
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pmd_frag = NULL;
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mm->context.pmd_frag = pmd_frag;
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}
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spin_unlock(&mm->page_table_lock);
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return (pmd_t *)ret;
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}
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static pmd_t *__alloc_for_pmdcache(struct mm_struct *mm)
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{
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void *ret = NULL;
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struct page *page;
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gfp_t gfp = GFP_KERNEL_ACCOUNT | __GFP_ZERO;
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if (mm == &init_mm)
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gfp &= ~__GFP_ACCOUNT;
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page = alloc_page(gfp);
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if (!page)
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return NULL;
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if (!pgtable_pmd_page_ctor(page)) {
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__free_pages(page, 0);
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return NULL;
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}
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atomic_set(&page->pt_frag_refcount, 1);
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ret = page_address(page);
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/*
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* if we support only one fragment just return the
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* allocated page.
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*/
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if (PMD_FRAG_NR == 1)
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return ret;
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spin_lock(&mm->page_table_lock);
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/*
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* If we find pgtable_page set, we return
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* the allocated page with single fragement
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* count.
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*/
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if (likely(!mm->context.pmd_frag)) {
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atomic_set(&page->pt_frag_refcount, PMD_FRAG_NR);
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mm->context.pmd_frag = ret + PMD_FRAG_SIZE;
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}
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spin_unlock(&mm->page_table_lock);
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return (pmd_t *)ret;
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}
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pmd_t *pmd_fragment_alloc(struct mm_struct *mm, unsigned long vmaddr)
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{
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pmd_t *pmd;
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pmd = get_pmd_from_cache(mm);
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if (pmd)
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return pmd;
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return __alloc_for_pmdcache(mm);
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}
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void pmd_fragment_free(unsigned long *pmd)
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{
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struct page *page = virt_to_page(pmd);
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if (PageReserved(page))
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return free_reserved_page(page);
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BUG_ON(atomic_read(&page->pt_frag_refcount) <= 0);
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if (atomic_dec_and_test(&page->pt_frag_refcount)) {
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pgtable_pmd_page_dtor(page);
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__free_page(page);
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}
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}
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static inline void pgtable_free(void *table, int index)
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{
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switch (index) {
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case PTE_INDEX:
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pte_fragment_free(table, 0);
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break;
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case PMD_INDEX:
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pmd_fragment_free(table);
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break;
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case PUD_INDEX:
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__pud_free(table);
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break;
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#if defined(CONFIG_PPC_4K_PAGES) && defined(CONFIG_HUGETLB_PAGE)
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/* 16M hugepd directory at pud level */
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case HTLB_16M_INDEX:
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BUILD_BUG_ON(H_16M_CACHE_INDEX <= 0);
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kmem_cache_free(PGT_CACHE(H_16M_CACHE_INDEX), table);
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break;
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/* 16G hugepd directory at the pgd level */
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case HTLB_16G_INDEX:
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BUILD_BUG_ON(H_16G_CACHE_INDEX <= 0);
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kmem_cache_free(PGT_CACHE(H_16G_CACHE_INDEX), table);
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break;
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#endif
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/* We don't free pgd table via RCU callback */
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default:
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BUG();
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}
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}
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void pgtable_free_tlb(struct mmu_gather *tlb, void *table, int index)
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{
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unsigned long pgf = (unsigned long)table;
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BUG_ON(index > MAX_PGTABLE_INDEX_SIZE);
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pgf |= index;
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tlb_remove_table(tlb, (void *)pgf);
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}
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void __tlb_remove_table(void *_table)
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{
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void *table = (void *)((unsigned long)_table & ~MAX_PGTABLE_INDEX_SIZE);
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unsigned int index = (unsigned long)_table & MAX_PGTABLE_INDEX_SIZE;
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return pgtable_free(table, index);
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}
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#ifdef CONFIG_PROC_FS
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atomic_long_t direct_pages_count[MMU_PAGE_COUNT];
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void arch_report_meminfo(struct seq_file *m)
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{
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/*
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* Hash maps the memory with one size mmu_linear_psize.
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* So don't bother to print these on hash
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*/
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if (!radix_enabled())
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return;
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seq_printf(m, "DirectMap4k: %8lu kB\n",
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atomic_long_read(&direct_pages_count[MMU_PAGE_4K]) << 2);
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seq_printf(m, "DirectMap64k: %8lu kB\n",
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atomic_long_read(&direct_pages_count[MMU_PAGE_64K]) << 6);
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seq_printf(m, "DirectMap2M: %8lu kB\n",
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atomic_long_read(&direct_pages_count[MMU_PAGE_2M]) << 11);
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seq_printf(m, "DirectMap1G: %8lu kB\n",
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atomic_long_read(&direct_pages_count[MMU_PAGE_1G]) << 20);
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}
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#endif /* CONFIG_PROC_FS */
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pte_t ptep_modify_prot_start(struct vm_area_struct *vma, unsigned long addr,
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pte_t *ptep)
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{
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unsigned long pte_val;
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/*
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* Clear the _PAGE_PRESENT so that no hardware parallel update is
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* possible. Also keep the pte_present true so that we don't take
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* wrong fault.
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*/
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pte_val = pte_update(vma->vm_mm, addr, ptep, _PAGE_PRESENT, _PAGE_INVALID, 0);
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return __pte(pte_val);
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}
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void ptep_modify_prot_commit(struct vm_area_struct *vma, unsigned long addr,
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pte_t *ptep, pte_t old_pte, pte_t pte)
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{
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if (radix_enabled())
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return radix__ptep_modify_prot_commit(vma, addr,
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ptep, old_pte, pte);
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set_pte_at(vma->vm_mm, addr, ptep, pte);
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}
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/*
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* For hash translation mode, we use the deposited table to store hash slot
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* information and they are stored at PTRS_PER_PMD offset from related pmd
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* location. Hence a pmd move requires deposit and withdraw.
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*
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* For radix translation with split pmd ptl, we store the deposited table in the
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* pmd page. Hence if we have different pmd page we need to withdraw during pmd
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* move.
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*
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* With hash we use deposited table always irrespective of anon or not.
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* With radix we use deposited table only for anonymous mapping.
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*/
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int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
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struct spinlock *old_pmd_ptl,
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struct vm_area_struct *vma)
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{
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if (radix_enabled())
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return (new_pmd_ptl != old_pmd_ptl) && vma_is_anonymous(vma);
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return true;
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}
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/*
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* Does the CPU support tlbie?
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*/
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bool tlbie_capable __read_mostly = true;
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EXPORT_SYMBOL(tlbie_capable);
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/*
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* Should tlbie be used for management of CPU TLBs, for kernel and process
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* address spaces? tlbie may still be used for nMMU accelerators, and for KVM
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* guest address spaces.
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*/
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bool tlbie_enabled __read_mostly = true;
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static int __init setup_disable_tlbie(char *str)
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{
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if (!radix_enabled()) {
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pr_err("disable_tlbie: Unable to disable TLBIE with Hash MMU.\n");
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return 1;
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}
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tlbie_capable = false;
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tlbie_enabled = false;
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return 1;
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}
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__setup("disable_tlbie", setup_disable_tlbie);
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static int __init pgtable_debugfs_setup(void)
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{
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if (!tlbie_capable)
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return 0;
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/*
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* There is no locking vs tlb flushing when changing this value.
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* The tlb flushers will see one value or another, and use either
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* tlbie or tlbiel with IPIs. In both cases the TLBs will be
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* invalidated as expected.
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*/
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debugfs_create_bool("tlbie_enabled", 0600,
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powerpc_debugfs_root,
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&tlbie_enabled);
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return 0;
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}
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arch_initcall(pgtable_debugfs_setup);
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