// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* This file contains the routines for flushing entries from the
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* TLB and MMU hash table.
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*
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* Derived from arch/ppc64/mm/init.c:
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
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* and Cort Dougan (PReP) (cort@cs.nmt.edu)
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* Copyright (C) 1996 Paul Mackerras
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*
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* Derived from "arch/i386/mm/init.c"
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* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
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*
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* Dave Engebretsen <engebret@us.ibm.com>
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* Rework for PPC64 port.
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*/
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/percpu.h>
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#include <linux/hardirq.h>
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#include <asm/tlbflush.h>
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#include <asm/tlb.h>
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#include <asm/bug.h>
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#include <asm/pte-walk.h>
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#include <trace/events/thp.h>
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DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
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/*
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* A linux PTE was changed and the corresponding hash table entry
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* neesd to be flushed. This function will either perform the flush
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* immediately or will batch it up if the current CPU has an active
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* batch on it.
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*/
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void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, unsigned long pte, int huge)
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{
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unsigned long vpn;
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struct ppc64_tlb_batch *batch = &get_cpu_var(ppc64_tlb_batch);
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unsigned long vsid;
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unsigned int psize;
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int ssize;
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real_pte_t rpte;
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int i, offset;
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i = batch->index;
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/*
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* Get page size (maybe move back to caller).
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*
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* NOTE: when using special 64K mappings in 4K environment like
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* for SPEs, we obtain the page size from the slice, which thus
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* must still exist (and thus the VMA not reused) at the time
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* of this call
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*/
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if (huge) {
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#ifdef CONFIG_HUGETLB_PAGE
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psize = get_slice_psize(mm, addr);
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/* Mask the address for the correct page size */
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addr &= ~((1UL << mmu_psize_defs[psize].shift) - 1);
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if (unlikely(psize == MMU_PAGE_16G))
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offset = PTRS_PER_PUD;
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else
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offset = PTRS_PER_PMD;
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#else
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BUG();
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psize = pte_pagesize_index(mm, addr, pte); /* shutup gcc */
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#endif
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} else {
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psize = pte_pagesize_index(mm, addr, pte);
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/*
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* Mask the address for the standard page size. If we
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* have a 64k page kernel, but the hardware does not
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* support 64k pages, this might be different from the
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* hardware page size encoded in the slice table.
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*/
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addr &= PAGE_MASK;
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offset = PTRS_PER_PTE;
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}
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/* Build full vaddr */
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if (!is_kernel_addr(addr)) {
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ssize = user_segment_size(addr);
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vsid = get_user_vsid(&mm->context, addr, ssize);
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} else {
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vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
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ssize = mmu_kernel_ssize;
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}
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WARN_ON(vsid == 0);
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vpn = hpt_vpn(addr, vsid, ssize);
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rpte = __real_pte(__pte(pte), ptep, offset);
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/*
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* Check if we have an active batch on this CPU. If not, just
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* flush now and return.
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*/
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if (!batch->active) {
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flush_hash_page(vpn, rpte, psize, ssize, mm_is_thread_local(mm));
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put_cpu_var(ppc64_tlb_batch);
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return;
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}
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/*
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* This can happen when we are in the middle of a TLB batch and
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* we encounter memory pressure (eg copy_page_range when it tries
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* to allocate a new pte). If we have to reclaim memory and end
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* up scanning and resetting referenced bits then our batch context
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* will change mid stream.
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*
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* We also need to ensure only one page size is present in a given
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* batch
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*/
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if (i != 0 && (mm != batch->mm || batch->psize != psize ||
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batch->ssize != ssize)) {
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__flush_tlb_pending(batch);
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i = 0;
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}
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if (i == 0) {
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batch->mm = mm;
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batch->psize = psize;
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batch->ssize = ssize;
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}
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batch->pte[i] = rpte;
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batch->vpn[i] = vpn;
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batch->index = ++i;
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if (i >= PPC64_TLB_BATCH_NR)
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__flush_tlb_pending(batch);
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put_cpu_var(ppc64_tlb_batch);
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}
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/*
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* This function is called when terminating an mmu batch or when a batch
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* is full. It will perform the flush of all the entries currently stored
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* in a batch.
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*
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* Must be called from within some kind of spinlock/non-preempt region...
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*/
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void __flush_tlb_pending(struct ppc64_tlb_batch *batch)
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{
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int i, local;
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i = batch->index;
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local = mm_is_thread_local(batch->mm);
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if (i == 1)
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flush_hash_page(batch->vpn[0], batch->pte[0],
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batch->psize, batch->ssize, local);
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else
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flush_hash_range(i, local);
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batch->index = 0;
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}
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void hash__tlb_flush(struct mmu_gather *tlb)
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{
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struct ppc64_tlb_batch *tlbbatch = &get_cpu_var(ppc64_tlb_batch);
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/*
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* If there's a TLB batch pending, then we must flush it because the
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* pages are going to be freed and we really don't want to have a CPU
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* access a freed page because it has a stale TLB
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*/
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if (tlbbatch->index)
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__flush_tlb_pending(tlbbatch);
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put_cpu_var(ppc64_tlb_batch);
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}
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/**
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* __flush_hash_table_range - Flush all HPTEs for a given address range
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* from the hash table (and the TLB). But keeps
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* the linux PTEs intact.
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*
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* @start : starting address
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* @end : ending address (not included in the flush)
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*
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* This function is mostly to be used by some IO hotplug code in order
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* to remove all hash entries from a given address range used to map IO
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* space on a removed PCI-PCI bidge without tearing down the full mapping
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* since 64K pages may overlap with other bridges when using 64K pages
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* with 4K HW pages on IO space.
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*
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* Because of that usage pattern, it is implemented for small size rather
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* than speed.
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*/
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void __flush_hash_table_range(unsigned long start, unsigned long end)
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{
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int hugepage_shift;
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unsigned long flags;
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start = ALIGN_DOWN(start, PAGE_SIZE);
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end = ALIGN(end, PAGE_SIZE);
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/*
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* Note: Normally, we should only ever use a batch within a
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* PTE locked section. This violates the rule, but will work
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* since we don't actually modify the PTEs, we just flush the
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* hash while leaving the PTEs intact (including their reference
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* to being hashed). This is not the most performance oriented
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* way to do things but is fine for our needs here.
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*/
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local_irq_save(flags);
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arch_enter_lazy_mmu_mode();
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for (; start < end; start += PAGE_SIZE) {
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pte_t *ptep = find_init_mm_pte(start, &hugepage_shift);
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unsigned long pte;
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if (ptep == NULL)
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continue;
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pte = pte_val(*ptep);
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if (!(pte & H_PAGE_HASHPTE))
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continue;
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hpte_need_flush(&init_mm, start, ptep, pte, hugepage_shift);
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}
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arch_leave_lazy_mmu_mode();
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local_irq_restore(flags);
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}
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void flush_tlb_pmd_range(struct mm_struct *mm, pmd_t *pmd, unsigned long addr)
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{
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pte_t *pte;
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pte_t *start_pte;
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unsigned long flags;
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addr = ALIGN_DOWN(addr, PMD_SIZE);
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/*
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* Note: Normally, we should only ever use a batch within a
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* PTE locked section. This violates the rule, but will work
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* since we don't actually modify the PTEs, we just flush the
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* hash while leaving the PTEs intact (including their reference
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* to being hashed). This is not the most performance oriented
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* way to do things but is fine for our needs here.
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*/
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local_irq_save(flags);
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arch_enter_lazy_mmu_mode();
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start_pte = pte_offset_map(pmd, addr);
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for (pte = start_pte; pte < start_pte + PTRS_PER_PTE; pte++) {
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unsigned long pteval = pte_val(*pte);
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if (pteval & H_PAGE_HASHPTE)
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hpte_need_flush(mm, addr, pte, pteval, 0);
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addr += PAGE_SIZE;
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}
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arch_leave_lazy_mmu_mode();
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local_irq_restore(flags);
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}
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