/*
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* Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
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*/
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#ifndef _ASM_POWERPC_PPC_ASM_H
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#define _ASM_POWERPC_PPC_ASM_H
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#include <linux/stringify.h>
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#include <asm/asm-compat.h>
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#include <asm/processor.h>
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#include <asm/ppc-opcode.h>
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#include <asm/firmware.h>
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#include <asm/feature-fixups.h>
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#ifdef __ASSEMBLY__
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#define SZL (BITS_PER_LONG/8)
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/*
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* Stuff for accurate CPU time accounting.
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* These macros handle transitions between user and system state
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* in exception entry and exit and accumulate time to the
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* user_time and system_time fields in the paca.
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*/
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#ifndef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
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#define ACCOUNT_CPU_USER_ENTRY(ptr, ra, rb)
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#define ACCOUNT_CPU_USER_EXIT(ptr, ra, rb)
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#define ACCOUNT_STOLEN_TIME
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#else
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#define ACCOUNT_CPU_USER_ENTRY(ptr, ra, rb) \
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MFTB(ra); /* get timebase */ \
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PPC_LL rb, ACCOUNT_STARTTIME_USER(ptr); \
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PPC_STL ra, ACCOUNT_STARTTIME(ptr); \
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subf rb,rb,ra; /* subtract start value */ \
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PPC_LL ra, ACCOUNT_USER_TIME(ptr); \
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add ra,ra,rb; /* add on to user time */ \
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PPC_STL ra, ACCOUNT_USER_TIME(ptr); \
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#define ACCOUNT_CPU_USER_EXIT(ptr, ra, rb) \
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MFTB(ra); /* get timebase */ \
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PPC_LL rb, ACCOUNT_STARTTIME(ptr); \
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PPC_STL ra, ACCOUNT_STARTTIME_USER(ptr); \
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subf rb,rb,ra; /* subtract start value */ \
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PPC_LL ra, ACCOUNT_SYSTEM_TIME(ptr); \
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add ra,ra,rb; /* add on to system time */ \
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PPC_STL ra, ACCOUNT_SYSTEM_TIME(ptr)
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#ifdef CONFIG_PPC_SPLPAR
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#define ACCOUNT_STOLEN_TIME \
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BEGIN_FW_FTR_SECTION; \
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beq 33f; \
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/* from user - see if there are any DTL entries to process */ \
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ld r10,PACALPPACAPTR(r13); /* get ptr to VPA */ \
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ld r11,PACA_DTL_RIDX(r13); /* get log read index */ \
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addi r10,r10,LPPACA_DTLIDX; \
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LDX_BE r10,0,r10; /* get log write index */ \
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cmpd cr1,r11,r10; \
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beq+ cr1,33f; \
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bl accumulate_stolen_time; \
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ld r12,_MSR(r1); \
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andi. r10,r12,MSR_PR; /* Restore cr0 (coming from user) */ \
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33: \
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END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
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#else /* CONFIG_PPC_SPLPAR */
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#define ACCOUNT_STOLEN_TIME
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#endif /* CONFIG_PPC_SPLPAR */
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#endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
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/*
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* Macros for storing registers into and loading registers from
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* exception frames.
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*/
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#ifdef __powerpc64__
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#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
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#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
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#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
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#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
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#else
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#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
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#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
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#define SAVE_NVGPRS(base) stmw 13, GPR0+4*13(base)
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#define REST_NVGPRS(base) lmw 13, GPR0+4*13(base)
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#endif
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#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
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#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
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#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
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#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
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#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
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#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
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#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
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#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
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#define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base)
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#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
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#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
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#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
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#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
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#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
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#define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base)
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#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
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#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
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#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
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#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
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#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
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#define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b
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#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
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#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
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#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
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#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
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#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
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#define REST_VR(n,b,base) li b,16*(n); lvx n,base,b
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#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
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#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
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#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
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#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
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#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
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#ifdef __BIG_ENDIAN__
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#define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base)
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#define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base)
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#else
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#define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \
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STXVD2X(n,b,base); \
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XXSWAPD(n,n)
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#define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \
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XXSWAPD(n,n)
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#endif
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/* Save the lower 32 VSRs in the thread VSR region */
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#define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b)
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#define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
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#define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
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#define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
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#define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
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#define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
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#define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b)
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#define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base)
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#define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
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#define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
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#define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
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#define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
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/*
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* b = base register for addressing, o = base offset from register of 1st EVR
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* n = first EVR, s = scratch
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*/
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#define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b)
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#define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o)
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#define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o)
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#define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o)
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#define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o)
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#define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o)
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#define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n
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#define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o)
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#define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o)
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#define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o)
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#define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o)
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#define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o)
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/* Macros to adjust thread priority for hardware multithreading */
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#define HMT_VERY_LOW or 31,31,31 # very low priority
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#define HMT_LOW or 1,1,1
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#define HMT_MEDIUM_LOW or 6,6,6 # medium low priority
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#define HMT_MEDIUM or 2,2,2
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#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
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#define HMT_HIGH or 3,3,3
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#define HMT_EXTRA_HIGH or 7,7,7 # power7 only
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#ifdef CONFIG_PPC64
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#define ULONG_SIZE 8
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#else
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#define ULONG_SIZE 4
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#endif
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#define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE))
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#define VCPU_GPR(n) __VCPU_GPR(__REG_##n)
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#ifdef __KERNEL__
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#ifdef CONFIG_PPC64
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#define STACKFRAMESIZE 256
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#define __STK_REG(i) (112 + ((i)-14)*8)
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#define STK_REG(i) __STK_REG(__REG_##i)
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#ifdef PPC64_ELF_ABI_v2
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#define STK_GOT 24
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#define __STK_PARAM(i) (32 + ((i)-3)*8)
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#else
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#define STK_GOT 40
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#define __STK_PARAM(i) (48 + ((i)-3)*8)
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#endif
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#define STK_PARAM(i) __STK_PARAM(__REG_##i)
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#ifdef PPC64_ELF_ABI_v2
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#define _GLOBAL(name) \
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.align 2 ; \
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.type name,@function; \
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.globl name; \
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name:
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#define _GLOBAL_TOC(name) \
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.align 2 ; \
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.type name,@function; \
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.globl name; \
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name: \
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0: addis r2,r12,(.TOC.-0b)@ha; \
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addi r2,r2,(.TOC.-0b)@l; \
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.localentry name,.-name
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#define DOTSYM(a) a
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#else
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#define XGLUE(a,b) a##b
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#define GLUE(a,b) XGLUE(a,b)
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#define _GLOBAL(name) \
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.align 2 ; \
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.globl name; \
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.globl GLUE(.,name); \
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.pushsection ".opd","aw"; \
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name: \
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.quad GLUE(.,name); \
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.quad .TOC.@tocbase; \
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.quad 0; \
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.popsection; \
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.type GLUE(.,name),@function; \
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GLUE(.,name):
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#define _GLOBAL_TOC(name) _GLOBAL(name)
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#define DOTSYM(a) GLUE(.,a)
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#endif
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#else /* 32-bit */
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#define _ENTRY(n) \
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.globl n; \
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n:
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#define _GLOBAL(n) \
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.stabs __stringify(n:F-1),N_FUN,0,0,n;\
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.globl n; \
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n:
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#define _GLOBAL_TOC(name) _GLOBAL(name)
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#endif
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/*
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* __kprobes (the C annotation) puts the symbol into the .kprobes.text
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* section, which gets emitted at the end of regular text.
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*
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* _ASM_NOKPROBE_SYMBOL and NOKPROBE_SYMBOL just adds the symbol to
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* a blacklist. The former is for core kprobe functions/data, the
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* latter is for those that incdentially must be excluded from probing
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* and allows them to be linked at more optimal location within text.
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*/
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#ifdef CONFIG_KPROBES
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#define _ASM_NOKPROBE_SYMBOL(entry) \
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.pushsection "_kprobe_blacklist","aw"; \
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PPC_LONG (entry) ; \
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.popsection
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#else
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#define _ASM_NOKPROBE_SYMBOL(entry)
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#endif
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#define FUNC_START(name) _GLOBAL(name)
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#define FUNC_END(name)
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/*
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* LOAD_REG_IMMEDIATE(rn, expr)
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* Loads the value of the constant expression 'expr' into register 'rn'
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* using immediate instructions only. Use this when it's important not
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* to reference other data (i.e. on ppc64 when the TOC pointer is not
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* valid) and when 'expr' is a constant or absolute address.
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*
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* LOAD_REG_ADDR(rn, name)
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* Loads the address of label 'name' into register 'rn'. Use this when
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* you don't particularly need immediate instructions only, but you need
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* the whole address in one register (e.g. it's a structure address and
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* you want to access various offsets within it). On ppc32 this is
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* identical to LOAD_REG_IMMEDIATE.
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*
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* LOAD_REG_ADDR_PIC(rn, name)
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* Loads the address of label 'name' into register 'run'. Use this when
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* the kernel doesn't run at the linked or relocated address. Please
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* note that this macro will clobber the lr register.
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*
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* LOAD_REG_ADDRBASE(rn, name)
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* ADDROFF(name)
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* LOAD_REG_ADDRBASE loads part of the address of label 'name' into
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* register 'rn'. ADDROFF(name) returns the remainder of the address as
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* a constant expression. ADDROFF(name) is a signed expression < 16 bits
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* in size, so is suitable for use directly as an offset in load and store
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* instructions. Use this when loading/storing a single word or less as:
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* LOAD_REG_ADDRBASE(rX, name)
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* ld rY,ADDROFF(name)(rX)
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*/
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/* Be careful, this will clobber the lr register. */
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#define LOAD_REG_ADDR_PIC(reg, name) \
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bl 0f; \
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0: mflr reg; \
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addis reg,reg,(name - 0b)@ha; \
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addi reg,reg,(name - 0b)@l;
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#if defined(__powerpc64__) && defined(HAVE_AS_ATHIGH)
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#define __AS_ATHIGH high
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#else
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#define __AS_ATHIGH h
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#endif
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.macro __LOAD_REG_IMMEDIATE_32 r, x
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.if (\x) >= 0x8000 || (\x) < -0x8000
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lis \r, (\x)@__AS_ATHIGH
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.if (\x) & 0xffff != 0
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ori \r, \r, (\x)@l
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.endif
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.else
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li \r, (\x)@l
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.endif
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.endm
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.macro __LOAD_REG_IMMEDIATE r, x
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.if (\x) >= 0x80000000 || (\x) < -0x80000000
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__LOAD_REG_IMMEDIATE_32 \r, (\x) >> 32
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sldi \r, \r, 32
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.if (\x) & 0xffff0000 != 0
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oris \r, \r, (\x)@__AS_ATHIGH
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.endif
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.if (\x) & 0xffff != 0
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ori \r, \r, (\x)@l
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.endif
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.else
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__LOAD_REG_IMMEDIATE_32 \r, \x
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.endif
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.endm
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#ifdef __powerpc64__
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#define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE reg, expr
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#define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr) \
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lis tmp, (expr)@highest; \
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lis reg, (expr)@__AS_ATHIGH; \
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ori tmp, tmp, (expr)@higher; \
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ori reg, reg, (expr)@l; \
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rldimi reg, tmp, 32, 0
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#define LOAD_REG_ADDR(reg,name) \
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ld reg,name@got(r2)
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#define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name)
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#define ADDROFF(name) 0
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/* offsets for stack frame layout */
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#define LRSAVE 16
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#else /* 32-bit */
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#define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE_32 reg, expr
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#define LOAD_REG_IMMEDIATE_SYM(reg,expr) \
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lis reg,(expr)@ha; \
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addi reg,reg,(expr)@l;
|
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#define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE_SYM(reg, name)
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#define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha
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#define ADDROFF(name) name@l
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/* offsets for stack frame layout */
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#define LRSAVE 4
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#endif
|
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/* various errata or part fixups */
|
#if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
|
#define MFTB(dest) \
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90: mfspr dest, SPRN_TBRL; \
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BEGIN_FTR_SECTION_NESTED(96); \
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cmpwi dest,0; \
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beq- 90b; \
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END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
|
#else
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#define MFTB(dest) MFTBL(dest)
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#endif
|
|
#ifdef CONFIG_PPC_8xx
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#define MFTBL(dest) mftb dest
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#define MFTBU(dest) mftbu dest
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#else
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#define MFTBL(dest) mfspr dest, SPRN_TBRL
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#define MFTBU(dest) mfspr dest, SPRN_TBRU
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#endif
|
|
#ifndef CONFIG_SMP
|
#define TLBSYNC
|
#else
|
#define TLBSYNC tlbsync; sync
|
#endif
|
|
#ifdef CONFIG_PPC64
|
#define MTOCRF(FXM, RS) \
|
BEGIN_FTR_SECTION_NESTED(848); \
|
mtcrf (FXM), RS; \
|
FTR_SECTION_ELSE_NESTED(848); \
|
mtocrf (FXM), RS; \
|
ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848)
|
#endif
|
|
/*
|
* This instruction is not implemented on the PPC 603 or 601; however, on
|
* the 403GCX and 405GP tlbia IS defined and tlbie is not.
|
* All of these instructions exist in the 8xx, they have magical powers,
|
* and they must be used.
|
*/
|
|
#if !defined(CONFIG_4xx) && !defined(CONFIG_PPC_8xx)
|
#define tlbia \
|
li r4,1024; \
|
mtctr r4; \
|
lis r4,KERNELBASE@h; \
|
.machine push; \
|
.machine "power4"; \
|
0: tlbie r4; \
|
.machine pop; \
|
addi r4,r4,0x1000; \
|
bdnz 0b
|
#endif
|
|
|
#ifdef CONFIG_IBM440EP_ERR42
|
#define PPC440EP_ERR42 isync
|
#else
|
#define PPC440EP_ERR42
|
#endif
|
|
/* The following stops all load and store data streams associated with stream
|
* ID (ie. streams created explicitly). The embedded and server mnemonics for
|
* dcbt are different so this must only be used for server.
|
*/
|
#define DCBT_BOOK3S_STOP_ALL_STREAM_IDS(scratch) \
|
lis scratch,0x60000000@h; \
|
dcbt 0,scratch,0b01010
|
|
/*
|
* toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them
|
* keep the address intact to be compatible with code shared with
|
* 32-bit classic.
|
*
|
* On the other hand, I find it useful to have them behave as expected
|
* by their name (ie always do the addition) on 64-bit BookE
|
*/
|
#if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64)
|
#define toreal(rd)
|
#define fromreal(rd)
|
|
/*
|
* We use addis to ensure compatibility with the "classic" ppc versions of
|
* these macros, which use rs = 0 to get the tophys offset in rd, rather than
|
* converting the address in r0, and so this version has to do that too
|
* (i.e. set register rd to 0 when rs == 0).
|
*/
|
#define tophys(rd,rs) \
|
addis rd,rs,0
|
|
#define tovirt(rd,rs) \
|
addis rd,rs,0
|
|
#elif defined(CONFIG_PPC64)
|
#define toreal(rd) /* we can access c000... in real mode */
|
#define fromreal(rd)
|
|
#define tophys(rd,rs) \
|
clrldi rd,rs,2
|
|
#define tovirt(rd,rs) \
|
rotldi rd,rs,16; \
|
ori rd,rd,((KERNELBASE>>48)&0xFFFF);\
|
rotldi rd,rd,48
|
#else
|
#define toreal(rd) tophys(rd,rd)
|
#define fromreal(rd) tovirt(rd,rd)
|
|
#define tophys(rd, rs) addis rd, rs, -PAGE_OFFSET@h
|
#define tovirt(rd, rs) addis rd, rs, PAGE_OFFSET@h
|
#endif
|
|
#ifdef CONFIG_PPC_BOOK3S_64
|
#define RFI rfid
|
#define MTMSRD(r) mtmsrd r
|
#define MTMSR_EERI(reg) mtmsrd reg,1
|
#else
|
#ifndef CONFIG_40x
|
#define RFI rfi
|
#else
|
#define RFI rfi; b . /* Prevent prefetch past rfi */
|
#endif
|
#define MTMSRD(r) mtmsr r
|
#define MTMSR_EERI(reg) mtmsr reg
|
#endif
|
|
#endif /* __KERNEL__ */
|
|
/* The boring bits... */
|
|
/* Condition Register Bit Fields */
|
|
#define cr0 0
|
#define cr1 1
|
#define cr2 2
|
#define cr3 3
|
#define cr4 4
|
#define cr5 5
|
#define cr6 6
|
#define cr7 7
|
|
|
/*
|
* General Purpose Registers (GPRs)
|
*
|
* The lower case r0-r31 should be used in preference to the upper
|
* case R0-R31 as they provide more error checking in the assembler.
|
* Use R0-31 only when really nessesary.
|
*/
|
|
#define r0 %r0
|
#define r1 %r1
|
#define r2 %r2
|
#define r3 %r3
|
#define r4 %r4
|
#define r5 %r5
|
#define r6 %r6
|
#define r7 %r7
|
#define r8 %r8
|
#define r9 %r9
|
#define r10 %r10
|
#define r11 %r11
|
#define r12 %r12
|
#define r13 %r13
|
#define r14 %r14
|
#define r15 %r15
|
#define r16 %r16
|
#define r17 %r17
|
#define r18 %r18
|
#define r19 %r19
|
#define r20 %r20
|
#define r21 %r21
|
#define r22 %r22
|
#define r23 %r23
|
#define r24 %r24
|
#define r25 %r25
|
#define r26 %r26
|
#define r27 %r27
|
#define r28 %r28
|
#define r29 %r29
|
#define r30 %r30
|
#define r31 %r31
|
|
|
/* Floating Point Registers (FPRs) */
|
|
#define fr0 0
|
#define fr1 1
|
#define fr2 2
|
#define fr3 3
|
#define fr4 4
|
#define fr5 5
|
#define fr6 6
|
#define fr7 7
|
#define fr8 8
|
#define fr9 9
|
#define fr10 10
|
#define fr11 11
|
#define fr12 12
|
#define fr13 13
|
#define fr14 14
|
#define fr15 15
|
#define fr16 16
|
#define fr17 17
|
#define fr18 18
|
#define fr19 19
|
#define fr20 20
|
#define fr21 21
|
#define fr22 22
|
#define fr23 23
|
#define fr24 24
|
#define fr25 25
|
#define fr26 26
|
#define fr27 27
|
#define fr28 28
|
#define fr29 29
|
#define fr30 30
|
#define fr31 31
|
|
/* AltiVec Registers (VPRs) */
|
|
#define v0 0
|
#define v1 1
|
#define v2 2
|
#define v3 3
|
#define v4 4
|
#define v5 5
|
#define v6 6
|
#define v7 7
|
#define v8 8
|
#define v9 9
|
#define v10 10
|
#define v11 11
|
#define v12 12
|
#define v13 13
|
#define v14 14
|
#define v15 15
|
#define v16 16
|
#define v17 17
|
#define v18 18
|
#define v19 19
|
#define v20 20
|
#define v21 21
|
#define v22 22
|
#define v23 23
|
#define v24 24
|
#define v25 25
|
#define v26 26
|
#define v27 27
|
#define v28 28
|
#define v29 29
|
#define v30 30
|
#define v31 31
|
|
/* VSX Registers (VSRs) */
|
|
#define vs0 0
|
#define vs1 1
|
#define vs2 2
|
#define vs3 3
|
#define vs4 4
|
#define vs5 5
|
#define vs6 6
|
#define vs7 7
|
#define vs8 8
|
#define vs9 9
|
#define vs10 10
|
#define vs11 11
|
#define vs12 12
|
#define vs13 13
|
#define vs14 14
|
#define vs15 15
|
#define vs16 16
|
#define vs17 17
|
#define vs18 18
|
#define vs19 19
|
#define vs20 20
|
#define vs21 21
|
#define vs22 22
|
#define vs23 23
|
#define vs24 24
|
#define vs25 25
|
#define vs26 26
|
#define vs27 27
|
#define vs28 28
|
#define vs29 29
|
#define vs30 30
|
#define vs31 31
|
#define vs32 32
|
#define vs33 33
|
#define vs34 34
|
#define vs35 35
|
#define vs36 36
|
#define vs37 37
|
#define vs38 38
|
#define vs39 39
|
#define vs40 40
|
#define vs41 41
|
#define vs42 42
|
#define vs43 43
|
#define vs44 44
|
#define vs45 45
|
#define vs46 46
|
#define vs47 47
|
#define vs48 48
|
#define vs49 49
|
#define vs50 50
|
#define vs51 51
|
#define vs52 52
|
#define vs53 53
|
#define vs54 54
|
#define vs55 55
|
#define vs56 56
|
#define vs57 57
|
#define vs58 58
|
#define vs59 59
|
#define vs60 60
|
#define vs61 61
|
#define vs62 62
|
#define vs63 63
|
|
/* SPE Registers (EVPRs) */
|
|
#define evr0 0
|
#define evr1 1
|
#define evr2 2
|
#define evr3 3
|
#define evr4 4
|
#define evr5 5
|
#define evr6 6
|
#define evr7 7
|
#define evr8 8
|
#define evr9 9
|
#define evr10 10
|
#define evr11 11
|
#define evr12 12
|
#define evr13 13
|
#define evr14 14
|
#define evr15 15
|
#define evr16 16
|
#define evr17 17
|
#define evr18 18
|
#define evr19 19
|
#define evr20 20
|
#define evr21 21
|
#define evr22 22
|
#define evr23 23
|
#define evr24 24
|
#define evr25 25
|
#define evr26 26
|
#define evr27 27
|
#define evr28 28
|
#define evr29 29
|
#define evr30 30
|
#define evr31 31
|
|
/* some stab codes */
|
#define N_FUN 36
|
#define N_RSYM 64
|
#define N_SLINE 68
|
#define N_SO 100
|
|
#define RFSCV .long 0x4c0000a4
|
|
/*
|
* Create an endian fixup trampoline
|
*
|
* This starts with a "tdi 0,0,0x48" instruction which is
|
* essentially a "trap never", and thus akin to a nop.
|
*
|
* The opcode for this instruction read with the wrong endian
|
* however results in a b . + 8
|
*
|
* So essentially we use that trick to execute the following
|
* trampoline in "reverse endian" if we are running with the
|
* MSR_LE bit set the "wrong" way for whatever endianness the
|
* kernel is built for.
|
*/
|
|
#ifdef CONFIG_PPC_BOOK3E
|
#define FIXUP_ENDIAN
|
#else
|
/*
|
* This version may be used in HV or non-HV context.
|
* MSR[EE] must be disabled.
|
*/
|
#define FIXUP_ENDIAN \
|
tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
|
b 191f; /* Skip trampoline if endian is good */ \
|
.long 0xa600607d; /* mfmsr r11 */ \
|
.long 0x01006b69; /* xori r11,r11,1 */ \
|
.long 0x00004039; /* li r10,0 */ \
|
.long 0x6401417d; /* mtmsrd r10,1 */ \
|
.long 0x05009f42; /* bcl 20,31,$+4 */ \
|
.long 0xa602487d; /* mflr r10 */ \
|
.long 0x14004a39; /* addi r10,r10,20 */ \
|
.long 0xa6035a7d; /* mtsrr0 r10 */ \
|
.long 0xa6037b7d; /* mtsrr1 r11 */ \
|
.long 0x2400004c; /* rfid */ \
|
191:
|
|
/*
|
* This version that may only be used with MSR[HV]=1
|
* - Does not clear MSR[RI], so more robust.
|
* - Slightly smaller and faster.
|
*/
|
#define FIXUP_ENDIAN_HV \
|
tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
|
b 191f; /* Skip trampoline if endian is good */ \
|
.long 0xa600607d; /* mfmsr r11 */ \
|
.long 0x01006b69; /* xori r11,r11,1 */ \
|
.long 0x05009f42; /* bcl 20,31,$+4 */ \
|
.long 0xa602487d; /* mflr r10 */ \
|
.long 0x14004a39; /* addi r10,r10,20 */ \
|
.long 0xa64b5a7d; /* mthsrr0 r10 */ \
|
.long 0xa64b7b7d; /* mthsrr1 r11 */ \
|
.long 0x2402004c; /* hrfid */ \
|
191:
|
|
#endif /* !CONFIG_PPC_BOOK3E */
|
|
#endif /* __ASSEMBLY__ */
|
|
/*
|
* Helper macro for exception table entries
|
*/
|
#define EX_TABLE(_fault, _target) \
|
stringify_in_c(.section __ex_table,"a";)\
|
stringify_in_c(.balign 4;) \
|
stringify_in_c(.long (_fault) - . ;) \
|
stringify_in_c(.long (_target) - . ;) \
|
stringify_in_c(.previous)
|
|
#ifdef CONFIG_PPC_FSL_BOOK3E
|
#define BTB_FLUSH(reg) \
|
lis reg,BUCSR_INIT@h; \
|
ori reg,reg,BUCSR_INIT@l; \
|
mtspr SPRN_BUCSR,reg; \
|
isync;
|
#else
|
#define BTB_FLUSH(reg)
|
#endif /* CONFIG_PPC_FSL_BOOK3E */
|
|
#endif /* _ASM_POWERPC_PPC_ASM_H */
|
