/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Support Power Management
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*
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* Copyright 2014-2015 Freescale Semiconductor Inc.
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*/
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#ifndef __PPC_FSL_PM_H
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#define __PPC_FSL_PM_H
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#define E500_PM_PH10 1
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#define E500_PM_PH15 2
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#define E500_PM_PH20 3
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#define E500_PM_PH30 4
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#define E500_PM_DOZE E500_PM_PH10
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#define E500_PM_NAP E500_PM_PH15
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#define PLAT_PM_SLEEP 20
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#define PLAT_PM_LPM20 30
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#define FSL_PM_SLEEP (1 << 0)
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#define FSL_PM_DEEP_SLEEP (1 << 1)
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struct fsl_pm_ops {
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/* mask pending interrupts to the RCPM from MPIC */
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void (*irq_mask)(int cpu);
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/* unmask pending interrupts to the RCPM from MPIC */
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void (*irq_unmask)(int cpu);
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void (*cpu_enter_state)(int cpu, int state);
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void (*cpu_exit_state)(int cpu, int state);
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void (*cpu_up_prepare)(int cpu);
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void (*cpu_die)(int cpu);
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int (*plat_enter_sleep)(void);
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void (*freeze_time_base)(bool freeze);
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/* keep the power of IP blocks during sleep/deep sleep */
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void (*set_ip_power)(bool enable, u32 mask);
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/* get platform supported power management modes */
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unsigned int (*get_pm_modes)(void);
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};
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extern const struct fsl_pm_ops *qoriq_pm_ops;
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int __init fsl_rcpm_init(void);
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#endif /* __PPC_FSL_PM_H */
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