// SPDX-License-Identifier: GPL-2.0-only
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/*
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* MPC8xx support functions
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*
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* Author: Scott Wood <scottwood@freescale.com>
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*
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* Copyright (c) 2007 Freescale Semiconductor, Inc.
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*/
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#include "ops.h"
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#include "types.h"
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#include "fsl-soc.h"
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#include "mpc8xx.h"
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#include "stdio.h"
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#include "io.h"
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#define MPC8XX_PLPRCR (0x284/4) /* PLL and Reset Control Register */
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/* Return system clock from crystal frequency */
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u32 mpc885_get_clock(u32 crystal)
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{
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u32 *immr;
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u32 plprcr;
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int mfi, mfn, mfd, pdf;
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u32 ret;
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immr = fsl_get_immr();
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if (!immr) {
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printf("mpc885_get_clock: Couldn't get IMMR base.\r\n");
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return 0;
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}
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plprcr = in_be32(&immr[MPC8XX_PLPRCR]);
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mfi = (plprcr >> 16) & 15;
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if (mfi < 5) {
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printf("Warning: PLPRCR[MFI] value of %d out-of-bounds\r\n",
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mfi);
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mfi = 5;
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}
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pdf = (plprcr >> 1) & 0xf;
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mfd = (plprcr >> 22) & 0x1f;
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mfn = (plprcr >> 27) & 0x1f;
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ret = crystal * mfi;
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if (mfn != 0)
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ret += crystal * mfn / (mfd + 1);
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return ret / (pdf + 1);
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}
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/* Set common device tree fields based on the given clock frequencies. */
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void mpc8xx_set_clocks(u32 sysclk)
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{
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void *node;
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dt_fixup_cpu_clocks(sysclk, sysclk / 16, sysclk);
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node = finddevice("/soc/cpm");
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if (node)
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setprop(node, "clock-frequency", &sysclk, 4);
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node = finddevice("/soc/cpm/brg");
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if (node)
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setprop(node, "clock-frequency", &sysclk, 4);
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}
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int mpc885_fixup_clocks(u32 crystal)
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{
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u32 sysclk = mpc885_get_clock(crystal);
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if (!sysclk)
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return 0;
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mpc8xx_set_clocks(sysclk);
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return 1;
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}
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