/*
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* T2081QDS Device Tree Source
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*
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* Copyright 2013 - 2015 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/include/ "t208xsi-pre.dtsi"
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/include/ "t208xqds.dtsi"
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/ {
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model = "fsl,T2081QDS";
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compatible = "fsl,T2081QDS";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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aliases {
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emi1_slot1 = &t2081mdio2;
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emi1_slot2 = &t2081mdio3;
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emi1_slot3 = &t2081mdio4;
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emi1_slot5 = &t2081mdio5;
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emi1_slot6 = &t2081mdio6;
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emi1_slot7 = &t2081mdio7;
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};
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};
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&soc {
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fman@400000 {
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ethernet@e0000 {
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phy-handle = <&phy_sgmii_s7_1c>;
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phy-connection-type = "sgmii";
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};
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ethernet@e2000 {
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phy-handle = <&phy_sgmii_s7_1d>;
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phy-connection-type = "sgmii";
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};
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ethernet@e4000 {
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phy-handle = <&rgmii_phy1>;
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phy-connection-type = "rgmii";
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};
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ethernet@e6000 {
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phy-handle = <&rgmii_phy2>;
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phy-connection-type = "rgmii";
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};
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ethernet@e8000 {
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phy-handle = <&phy_sgmii_s3_1c>;
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phy-connection-type = "sgmii";
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};
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ethernet@ea000 {
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phy-handle = <&phy_sgmii_s7_1f>;
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phy-connection-type = "sgmii";
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};
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ethernet@f0000 {
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phy-handle = <&phy_sgmii_s2_1c>;
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phy-connection-type = "xgmii";
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};
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ethernet@f2000 {
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phy-handle = <&phy_sgmii_s7_1e>;
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phy-connection-type = "xgmii";
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};
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};
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};
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&boardctrl {
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mdio-mux-emi1 {
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compatible = "mdio-mux-mmioreg", "mdio-mux";
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mdio-parent-bus = <&mdio0>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x54 1>;
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mux-mask = <0xe0>;
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t2081mdio0: mdio@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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rgmii_phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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};
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t2081mdio1: mdio@20 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x20>;
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rgmii_phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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};
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t2081mdio2: mdio@40 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40>;
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phy_sgmii_s1_1c: ethernet-phy@1c {
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reg = <0x1c>;
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};
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phy_sgmii_s1_1d: ethernet-phy@1d {
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reg = <0x1d>;
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};
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phy_sgmii_s1_1e: ethernet-phy@1e {
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reg = <0x1e>;
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};
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phy_sgmii_s1_1f: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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t2081mdio3: mdio@60 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x60>;
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phy_sgmii_s2_1c: ethernet-phy@1c {
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reg = <0x1c>;
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};
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phy_sgmii_s2_1d: ethernet-phy@1d {
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reg = <0x1d>;
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};
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phy_sgmii_s2_1e: ethernet-phy@1e {
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reg = <0x1e>;
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};
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phy_sgmii_s2_1f: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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t2081mdio4: mdio@80 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x80>;
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status = "disabled";
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phy_sgmii_s3_1c: ethernet-phy@1c {
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reg = <0x1c>;
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};
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phy_sgmii_s3_1d: ethernet-phy@1d {
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reg = <0x1d>;
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};
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phy_sgmii_s3_1e: ethernet-phy@1e {
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reg = <0x1e>;
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};
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phy_sgmii_s3_1f: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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t2081mdio5: mdio@a0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xa0>;
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status = "disabled";
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phy_sgmii_s5_1c: ethernet-phy@1c {
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reg = <0x1c>;
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};
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phy_sgmii_s5_1d: ethernet-phy@1d {
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reg = <0x1d>;
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};
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phy_sgmii_s5_1e: ethernet-phy@1e {
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reg = <0x1e>;
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};
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phy_sgmii_s5_1f: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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t2081mdio6: mdio@c0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xc0>;
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status = "disabled";
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phy_sgmii_s6_1c: ethernet-phy@1c {
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reg = <0x1c>;
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};
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phy_sgmii_s6_1d: ethernet-phy@1d {
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reg = <0x1d>;
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};
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phy_sgmii_s6_1e: ethernet-phy@1e {
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reg = <0x1e>;
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};
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phy_sgmii_s6_1f: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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t2081mdio7: mdio@e0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xe0>;
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phy_sgmii_s7_1c: ethernet-phy@1c {
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reg = <0x1c>;
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};
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phy_sgmii_s7_1d: ethernet-phy@1d {
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reg = <0x1d>;
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};
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phy_sgmii_s7_1e: ethernet-phy@1e {
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reg = <0x1e>;
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};
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phy_sgmii_s7_1f: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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};
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};
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/include/ "t2081si-post.dtsi"
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