/*
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* T104xQDS Device Tree Source
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*
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* Copyright 2013 - 2015 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/ {
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model = "fsl,T1040QDS";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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aliases {
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emi1_rgmii0 = &t1040mdio0;
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emi1_rgmii1 = &t1040mdio1;
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emi1_slot3 = &t1040mdio3;
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emi1_slot5 = &t1040mdio5;
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emi1_slot6 = &t1040mdio6;
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emi1_slot7 = &t1040mdio7;
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rgmii_phy1 = &rgmii_phy1;
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rgmii_phy2 = &rgmii_phy2;
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phy_s3_01 = &phy_s3_01;
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phy_s3_02 = &phy_s3_02;
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phy_s3_03 = &phy_s3_03;
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phy_s3_04 = &phy_s3_04;
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phy_s5_01 = &phy_s5_01;
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phy_s5_02 = &phy_s5_02;
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phy_s5_03 = &phy_s5_03;
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phy_s5_04 = &phy_s5_04;
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phy_s6_01 = &phy_s6_01;
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phy_s6_02 = &phy_s6_02;
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phy_s6_03 = &phy_s6_03;
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phy_s6_04 = &phy_s6_04;
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phy_s7_01 = &phy_s7_01;
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phy_s7_02 = &phy_s7_02;
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phy_s7_03 = &phy_s7_03;
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phy_s7_04 = &phy_s7_04;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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bman_fbpr: bman-fbpr {
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size = <0 0x1000000>;
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alignment = <0 0x1000000>;
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};
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qman_fqd: qman-fqd {
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size = <0 0x400000>;
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alignment = <0 0x400000>;
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};
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qman_pfdr: qman-pfdr {
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size = <0 0x2000000>;
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alignment = <0 0x2000000>;
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};
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};
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ifc: localbus@ffe124000 {
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reg = <0xf 0xfe124000 0 0x2000>;
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ranges = <0 0 0xf 0xe8000000 0x08000000
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2 0 0xf 0xff800000 0x00010000
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3 0 0xf 0xffdf0000 0x00008000>;
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x8000000>;
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bank-width = <2>;
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device-width = <1>;
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};
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nand@2,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,ifc-nand";
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reg = <0x2 0x0 0x10000>;
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};
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board-control@3,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,fpga-qixis";
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reg = <3 0 0x300>;
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ranges = <0 3 0 0x300>;
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mdio-mux-emi1 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mdio-mux-mmioreg", "mdio-mux";
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mdio-parent-bus = <&mdio0>;
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reg = <0x54 1>;
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mux-mask = <0xe0>;
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t1040mdio0: mdio@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x00>;
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status = "disabled";
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rgmii_phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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};
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t1040mdio1: mdio@20 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x20>;
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status = "disabled";
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rgmii_phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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};
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t1040mdio3: mdio@60 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x60>;
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status = "disabled";
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phy_s3_01: ethernet-phy@1c {
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reg = <0x1c>;
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};
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phy_s3_02: ethernet-phy@1d {
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reg = <0x1d>;
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};
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phy_s3_03: ethernet-phy@1e {
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reg = <0x1e>;
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};
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phy_s3_04: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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t1040mdio5: mdio@a0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xa0>;
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phy_s5_01: ethernet-phy@1c {
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reg = <0x14>;
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};
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phy_s5_02: ethernet-phy@1d {
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reg = <0x15>;
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};
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phy_s5_03: ethernet-phy@1e {
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reg = <0x16>;
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};
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phy_s5_04: ethernet-phy@1f {
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reg = <0x17>;
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};
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};
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t1040mdio6: mdio@c0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xc0>;
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phy_s6_01: ethernet-phy@1c {
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reg = <0x18>;
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};
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phy_s6_02: ethernet-phy@1d {
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reg = <0x19>;
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};
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phy_s6_03: ethernet-phy@1e {
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reg = <0x1a>;
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};
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phy_s6_04: ethernet-phy@1f {
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reg = <0x1b>;
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};
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};
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t1040mdio7: mdio@e0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xe0>;
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status = "disabled";
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phy_s7_01: ethernet-phy@1c {
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reg = <0x1c>;
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};
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phy_s7_02: ethernet-phy@1d {
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reg = <0x1d>;
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};
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phy_s7_03: ethernet-phy@1e {
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reg = <0x1e>;
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};
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phy_s7_04: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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};
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};
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};
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memory {
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device_type = "memory";
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};
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dcsr: dcsr@f00000000 {
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ranges = <0x00000000 0xf 0x00000000 0x01072000>;
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};
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bportals: bman-portals@ff4000000 {
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ranges = <0x0 0xf 0xf4000000 0x2000000>;
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};
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qportals: qman-portals@ff6000000 {
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ranges = <0x0 0xf 0xf6000000 0x2000000>;
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};
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soc: soc@ffe000000 {
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ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
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reg = <0xf 0xfe000000 0 0x00001000>;
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spi@110000 {
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,n25q128a11", "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>; /* input clock */
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};
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};
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i2c@118000 {
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pca9547@77 {
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compatible = "nxp,pca9547";
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reg = <0x77>;
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};
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rtc@68 {
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compatible = "dallas,ds3232";
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reg = <0x68>;
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interrupts = <0x1 0x1 0 0>;
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};
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};
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fman@400000 {
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ethernet@e0000 {
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fixed-link = <0 1 1000 0 0>;
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phy-connection-type = "sgmii";
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};
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ethernet@e2000 {
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fixed-link = <1 1 1000 0 0>;
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phy-connection-type = "sgmii";
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};
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ethernet@e4000 {
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phy-handle = <&phy_s7_03>;
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phy-connection-type = "sgmii";
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};
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ethernet@e6000 {
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phy-handle = <&rgmii_phy1>;
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phy-connection-type = "rgmii";
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};
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ethernet@e8000 {
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phy-handle = <&rgmii_phy2>;
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phy-connection-type = "rgmii";
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};
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};
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};
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pci0: pcie@ffe240000 {
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reg = <0xf 0xfe240000 0 0x10000>;
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ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x10000000
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0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
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pcie@0 {
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ranges = <0x02000000 0 0xe0000000
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0x02000000 0 0xe0000000
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0 0x10000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00010000>;
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};
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};
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pci1: pcie@ffe250000 {
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reg = <0xf 0xfe250000 0 0x10000>;
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ranges = <0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
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0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
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pcie@0 {
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ranges = <0x02000000 0 0xe0000000
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0x02000000 0 0xe0000000
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0 0x10000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00010000>;
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};
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};
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pci2: pcie@ffe260000 {
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reg = <0xf 0xfe260000 0 0x10000>;
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ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
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0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
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pcie@0 {
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ranges = <0x02000000 0 0xe0000000
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0x02000000 0 0xe0000000
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0 0x10000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00010000>;
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};
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};
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pci3: pcie@ffe270000 {
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reg = <0xf 0xfe270000 0 0x10000>;
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ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
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0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
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pcie@0 {
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ranges = <0x02000000 0 0xe0000000
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0x02000000 0 0xe0000000
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0 0x10000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00010000>;
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};
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};
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qe: qe@ffe140000 {
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ranges = <0x0 0xf 0xfe140000 0x40000>;
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reg = <0xf 0xfe140000 0 0x480>;
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brg-frequency = <0>;
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bus-frequency = <0>;
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si1: si@700 {
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compatible = "fsl,t1040-qe-si";
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reg = <0x700 0x80>;
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};
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siram1: siram@1000 {
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compatible = "fsl,t1040-qe-siram";
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reg = <0x1000 0x800>;
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};
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ucc_hdlc: ucc@2000 {
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compatible = "fsl,ucc-hdlc";
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rx-clock-name = "clk8";
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tx-clock-name = "clk9";
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fsl,rx-sync-clock = "rsync_pin";
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fsl,tx-sync-clock = "tsync_pin";
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fsl,tx-timeslot-mask = <0xfffffffe>;
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fsl,rx-timeslot-mask = <0xfffffffe>;
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fsl,tdm-framer-type = "e1";
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fsl,tdm-id = <0>;
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fsl,siram-entry-id = <0>;
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fsl,tdm-interface;
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};
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ucc_serial: ucc@2200 {
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compatible = "fsl,t1040-ucc-uart";
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port-number = <0>;
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rx-clock-name = "brg2";
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tx-clock-name = "brg2";
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};
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};
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};
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